나노기술 환경에 적합한 차세대 정보 보호 프로세서 구조와 연산 회로 기술 연구 |
최병윤
(동의대학교 컴퓨터공학과)
이종형 (동의대학교 전자공학과) 조현숙 (한국전자통신연구원 정보보호기반연구팀) |
1 |
An Algorithm-Agile Cryptographic Co-Processor based on FPGAs
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2 |
Towards Nanocomputer Architecture
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3 |
Globally-aynchronous, locally-synchronous systems
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4 |
How secure are FPGAs in Cryptographic Applications? (Long Version)
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6 |
Novel processor arrays for nanoelectronics
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7 |
Aspect of Systems and Circuits for Nanoelectronics
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DOI ScienceOn |
8 |
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9 |
The future of the Art of Cryptographic Implementations
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10 |
A High Performance Flexible Architecture for Cryptography
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11 |
System and Circuit Aspect of Nanoelectronics
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12 |
From Micro- To Nano- Technologies
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13 |
Device Scaling Limits of si MOSFETs and Their Application Dependencies
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DOI ScienceOn |
14 |
VLSI array processor
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15 |
What makes a good computer device ?
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DOI |
16 |
Defect tolerance in VLSI circuits
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DOI ScienceOn |
17 |
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18 |
Binary adder architectures for cell-Based VLSI and their synthesis
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19 |
The use of nano-electronic devices in highly parallel computing systems
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DOI ScienceOn |
20 |
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21 |
CMOS scaling for highper-formance and low-power-the next ten years
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22 |
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23 |
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