• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9B
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• pp.1683-1689
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• 1999

We have implemented Frequency bandwidth expander with frequency upconverting by VCO drift canceller and comb generator. Te output of the low frequency synthesizer which the output frequency is 220~280MHz(Resolution : 5MHz) is expanded to 1660~2140MHz by this system. The phase noise of this system only depends on the phase noise of comb generator and low frequency synthesizer. The phase noise of VCO don’t influence at the frequency expander because the drift of VCO cancel out. When we control the output of VCO, the output frequency of this system is varied by 60MHz x N as filter banker. The switching time and the spurious of the frequency expander is below 3usec, -55dBc respectively. This system easily expands bandwidth additively by expanding the output bandwidth of the VCO. We can apply the frequency expander to very wide band microwave synthesizer which has fast switching time.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.333-341
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• 2015

In this paper, a 0.5~4 GHz frequency synthesizer having good phase noise performance is proposed. Wideband output frequencies of the synthesizer were synthesized using DDS(Direct Digital Synthesizer) and analog direct frequency synthesis technology in order to obtain fast settling time. Also in order to get good phase noise performance, 2.4 GHz DDS clock was generated by VCO(Voltage Controlled Oscillator) which was locked by the 100 MHz reference oscillator using SPD(Sample Phase Detector). The phase noise performance of wideband frequency synthesizer was estimated and the results were compared with the measured ones. The measured phase noise of the frequency synthesizer was less then -121 dBc @ 100 kHz at 4 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.941-947
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• 2017

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.8
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• pp.717-724
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• 2016

This paper presents design of a 40 GHz CMOS PLL frequency synthesizer for a 60 GHz sliding-IF RF transceiver. For stable locking over a wide bandwith for a injection-locked frequency divider, an inductive-peaking technique is employed so that it ensures the PLL can safely lock across the very wide tuning range of the VCO. Also, Injection-locked type LC-buffer with low-phase noise and low-power consumption is added in between the VCO and ILFD so that it can block any undesirable interaction and performance degradation between VCO and ILFD. The PLL is designed in 65 nm CMOS precess. It covers from 37.9 to 45.3 GHz of the output frequency. and its power consumption is 74 mA from 1.2 V power supply.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2002.07a
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• pp.215-220
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• 2002

마모가 잘 되는 현미기 고무롤러의 단점을 보완하여 작업의 효율화를 위해 내마모성이 높은 재질인 합성우레탄으로 현미기용 롤러를 개발하여 시험하였다. 가. 경도별 합성우레탄의 마모량을 테이버식으로 측정한 결과 경도80$^{\circ}$, 85$^{\circ}$에서 각각 68, 72mg으로 낮게 나타났으나 현미기롤러 재질로 적용하기 위해서는 탈부 요인시험이 요구되었다. 나. 합성우레탄롤러의 적정경도 구명요인시험을 실시한 결과 탈부율 및 동할률이 경도 80$^{\circ}$이상에서 기존의 고무롤러에 비해 동등하거나 우수한 것으로 나타났다. 다. 현장 적용 성능시험결과 고무롤러의 경우 벼 가공량이 300톤/조 이었고, 합성우레탄롤러 경도 85$^{\circ}$의 경우 1,083톤/조로 내구성이 3.6배 큰 것으로 나타났다. 라, 고무롤러의 동할율 증가량은 0.43%인데 비해 합성우레탄롤러는 경도 85$^{\circ}$에서 0.29%로 나타나 현미품위가 향상되었다. 마, 위 결과를 종합하여볼 때 합성우레탄 현미기롤러의 경도는 85$^{\circ}$ 가장 적합한 것으로 나타났다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.191-200
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• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.6
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• pp.959-968
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• 2000

In this paper, a low phase noise frequency synthesizer used to TX local oscillator in BWLL RF tranceiver is presented. The phase-locked stable 25GHz-band frequencies in BWLL TX LO are obtained by using 2 GHz baseband frequency synthesizer, sixth-harmonic frequency multiplier and frequency doubler at 12 GHz band frequency input. The 25 GHz band frequency synthesizer presented in this paper has 3-output frequencies at 24.92 GHz, 25.10 GHz, 25.26 GHz. At 24.92 GHz frequency the synthesizer has 0.44 dBm output power and shows -87.93 dBc/Hz(a 10 KHz), -109.54 dBc/Hz (a100 KHz) phase noise characteristics .

• Journal of the Earthquake Engineering Society of Korea
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• v.4 no.4
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• pp.53-61
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• 2000

능동 제어기를 설계하기 위해서는 제어대상 구조물의 수학모델의 구해야한다. 그러나, 무한차원의 구조물에 대하여 정확한 모델을 구하는 것은 불가능하므로 유한차원인 저차원화된 모델을 사용하여 제어기를 설계한다. 그러나, 실제 구조물과 저차원화된 모델사이의 오차에 의하여 제어기의 성능이 저하가 되면 제어기와 구조물의 상호작용, 지진과 같은 오란 등의 불확실성, 지진시 구조물의 동적 특성 변화로 인하여 제어기의 성능이 더욱 저하가 된다. 이러한 저하 요인은 제어기 설계시 요구되는 구조물의 수학모델에 대한 불확실한 요소로 작용하기 때문에 제어성능의 저하를 일으키며 응답의 불안정을 유발하기로 한다. 본 연구에서는 질량형 능동제어기(AMD)가 설치된 3층 건물 모형의 모델 오차에 관한 불확실성을 반영한 강인제어기법을 적용하여 제어성능과 안정성을 실험을 통하여 분석하였다. 강인제어 기법인 $\mu$ 합성법에 요구되는 여러 가지 가중함수인 주파수필터는 건물과 AMD의 특성, 모델 오차, 제어율과 AMD 성능의 , 측정잡음 및 지진외란의 특성 등을 고려하여 정량적으로 선택되었다. $\mu$합성법에 의하여 제어기를 설계하였으며 강인성을 비교하기 위하여 불확실성이 고려되지 않는 LQG 기법에 의한 제어기를 선택하였다. $\mu$합성법은 규정된 불확성에 대하여 제어의 강인성을 가지므로 동적특성이 바뀐 건물모형에 관한 강인성을 LQG 기법에 의한 제어성능과 비교하였다. 그 결과 동적특성이 변화된 건물에 대하여 $\mu$합성법만이 제어의 효율성이 유지되는 강인성을 나타내었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.152-158
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• 2004

A low phase noise frequency synthesizer at X-Band which employs the subharmonic injection locking was designed and tested. The designed frequency synthesizer consists of a 1.75 GHz master oscillator - which also operates as a harmonic generator - and a 10.5 GHz slave oscillator. A 1.75 GHz master oscillator based on PLL technique used two transistors - one constitutes the active part of VCO and the other operates as a buffer amplifier as well as harmonic generator. The first stage operates a fixed locked oscillator and using the BJT transistor whose cutoff frequency is 45 GHz, the second stage is designed, operating as a harmonic generator. The 6th harmonic which is produced from the harmonic generator is injected into the following slave oscillator which also behaves as an amplifier having about 45 dB gain. The realized frequency synthesizer has a 7.4 V/49 mA, -0.5 V/4 mA of the low DC power consumption, 4.53 dBm of output power, and a phase noise of -95.09 dBc/Hz and -108.90 dBc/Hz at the 10 kHz and 100 kHz offset frequency, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2409-2418
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• 2013

Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.