• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.425-426
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• 2008

본 논문에서 설계한 802.11 MAC(Medium Access Control)은 하드웨어와 소프트웨어의 통합 구조로 되어 있다. MAC에서 가장 빠르게 동작해야 하는 프레임 전송과 수신블록은 하드웨어로 설계를 하였고, 그 외에는 소프트웨어로 설계가 되었다. 하드웨어로 설계된 MAC은 802.11 표준문서에 포함된 SDL(Specification and Description Language)을 기초하여 설계하였으며, 성능 향상을 위하여 수신블록의 중복 프레임 검사를 수행하는 블록과 프레임을 분석하여 정보를 추출하는 블록을 SDL과 다르게 설계 하였다. 삼성 0.35공정 라이브러리를 이용하여 합성한 결과 3만 게이트의 크기를 갖으며, 최대 동작 주파수는 100MHz이다. 메모리는 47Kbits SRAM을 사용하였다. 실제동작의 검증에 앞서 Mentor Graphics사의 ModelSim을 이용하여 시뮬레이션을 수행하였으며, 동작 검증은 Huins 사의 Altera Excalibur FPGA가 탑재된 XP8000 보드를 이용하여 이루어 졌다.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.879-882
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• 1998

본 논문에서는 리드 피치가 15mil인 208핀 QFP칩을 검사하는 고해상도의 비젼 모델 시스템을 개발하였다. 전체적인 하드웨어와 고해상도에 적합한 알고리즘 및 이를 실현하는 프로그램을 개발하였으며, 특히 칩 리드 검출을 위한 새로운 알고리즘을 제안하였다. 본 논문에서는 제안한 방법의 특징은 조명의 간섭에 대해 강하며 검사 속도 및 정밀도가 향상되었다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.881-883
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• 2003

하드웨어 검증과 모델 체킹 등의 분야에서, SAT(satisfiability problem)나 항진 명제 검사(tautology checking)는 매우 중요한 문제이다. 그러나 이들은 모두 NP-complete 문제이므로 그 복잡도가 매우 크다. 이를 해결하기 위해 여러 가지 연구가 이루어져 왔으며, 여러 효율적인 알고리즘이 존재한다. 이러한 알고리즘은 대부분 일반 표현식을 CNF(conjunctive normal form)로 바꾸어 입력 형식으로 사용한다. 이 논문에서는 일반 표현식을 입력으로 받아 DNF로 변환한 뒤 DNF의 특성을 이용하여 SAT를 검사하는 효율적인 방법을 제시한다.

• Journal of the Korean Society for Nondestructive Testing
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• v.32 no.5
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• pp.540-544
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• 2012

Like the phase array based ultrasonic system, complicated electronics has been used for real time signal processing in the magnetostrictive long-range ultrasonic testing(LRUT) system. This study shows that the software approach including the phase compensation, noise filtering and waveform transformation takes advantage rather than the previous hardware approach. Furthermore, it is possible for the software approach to be able more flexible and efficient realtime signal processing. These results will contribute to a cost-effective LRUT system and analysis of the inspection data.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.1-8
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• 2008

An occlusion culling method, one of visibility culling methods, excludes invisible objects or triangles which are covered by other objects. As it reduces computation quantity, occlusion culling is an effective method to handle complex scenes in real-time. But an existing common occlusion culling method, such as hardware occlusion query method, sends objects' data twice to GPU and this causes processing overheads once for occlusion culling test and the other is for rendering. And another existing hardware occlusion culling method, VCBP, can test objects' visibility quickly, but it neither test bounding volume nor return test result to application stage. In this paper, we propose a single pass occlusion culling method which uses temporal and spatial coherency, with effective occlusion culling hardware architecture. In our approach, the hardware performs occlusion culling test rapidly with cache on the rasterization stage where triangles are transformed into fragments. At the same time, hardware sends each primitive's visibility information to application stage. As a result, the application stage reduces data transmission quantity by excluding covered objects using the visibility information on previous frame and hierarchical spatial tree. Our proposed method improved maximum 44%, minimum 14% compared with S&W method based on hardware occlusion query. And the performance is increased 25% and 17% respectively, compared to maximum and minimum performance of CHC method which is based on occlusion culling method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.520-523
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• 2008

As a result of the recent development of the electro-information industry, the hardware of an automated ultrasonic testing system is getting lighter and diversified image processing techniques are applied to its software so that the possible precise totaling and detecting of the flaws are studied. This study proposes an automated ultrasonic testing system of the pipe in order to organize the optimized system, and also describes the data flow and general composition of the software for the design of the system.

• Journal of the Korean Society for Nondestructive Testing
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• v.28 no.4
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• pp.331-338
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• 2008

Ultrasonic testing for welds is widely used to ensure the integrity of facilities in NPPs. Automated ultrasonic testing(AUT) is more consistent than the manual ultrasonic testing(MUT). It can scan welded parts, examines the scanned images, and saves the results as data files. AUT in NPPs is making use of commercial systems, and there has been some difficulties in calibration of the system. An AUT system is developed. It comprises of pulser/receiver, scanner and a control program(SonicWizard). The performance demonstration for piping welds in NPPs and the piping wall thickness measurement on site were conducted to verify this system. The test results of the ultrasonic testing system developed is satisfactory and effective.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.329-334
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• 2002

For the testability, this paper proposed the algorithm at autonomous synthesis which includes the data path structure as the self testing as possible on high level synthesis method when VHDL, coding is used in the system design area. In the proposed algorithm of this paper, MUXs and registers are assigned to the data path of designed system. And the designed data path could be mapped the H/W specification of described VHDL coding to the testable library. As a results, it was mapped H/W to the assign algorithm that is minimized MUX and the registers in collision graph.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.22-27
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• 2009

In this paper, an automatic functional inspection system EVT (Emulated Vision Tester) for LCD drive module PCB has been proposed and implemented. Typical automatic inspection system such as probing methods and vision-based systems are widely known and used, however, there exist undetectable defects due to critical timing factors which they may miss to catch from LCD equipments. Especially typical vision-based systems have inconsistency on acquisition of images so that distinction between gray scales can be difficult which results in low level of performance and reliability on the inspection results. The proposed EVT system is pure hardware solution. It directly compares pattern signals from a pattern generator to output signals from LCD drive module. It also inspects variety of analog signals such as voltage, resistance, wave forms and so forth. The EVT system not only shows high performance in terms of reliability and processing speed but reduces costs on inspection and maintenance. Also, full automation of entire production line can be realized when EVT is applied in in-line inspection processes.