• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.4
• /
• pp.17-23
• /
• 2013

As a basic research to develop stretchable electronic packaging technology, CNT-Ag composite pads were formed on top of Cu/Sn chip bumps and flip-chip bonded using anisotropic conductive adhesive. Average contact resistances of the flip-chip joints were measured with respect to bonding pressure and presence of the CNT-Ag composite pads. When Cu/Sn chip bumps with CNT-Ag composite pads were flip-chip bonded to substrate Cu pads at 25MPa or 50 MPa, contact resistance was too high to measure. The specimen processed by flip-chip bonding the Cu/Sn chip bumps with CNT-Ag composite pads to the substrate Cu pads exhibited an average contact resistance of $213m{\Omega}$. On the other hand, the flip-chip specimens processed by bonding Cu/Sn chip bumps without CNT-Ag composite pads to substrate Cu pads at 25MPa, 50MPa, and 100MPa exhibited average contact resistances of $370m{\Omega}$, $372m{\Omega}$, and $112m{\Omega}$, respectively.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2011.05a
• /
• pp.64.1-64.1
• /
• 2011

LCD 디스플레이 등에 사용되는 글래스 패널 위에 bare si die를 직접 실장하는 COG 플립칩 패키지의 경우 Au 범프와 ITO 패드 간의 전기적 접속 및 접합부 신뢰성 확보를 위해 접속소재로서 ACF (anisotropic conductive film)가 사용되고 있다. 그러나 ACF는 고가이고 접속피치 미세화에 따라 브릿지 형상에 의한 쇼트 등의 문제가 발행할 수 있어 NCP (non-conductive paste)의 상용화가 요구되고 있다. 본 연구에서는 NCP를 적용한 COG 패키지에 있어서 온도, 압력 등의 열압착 본딩 조건과 NCP 물성이 Au-ITO 접합부의 전기적 및 기계적 특성에 미치는 영향을 조사하였다. NCP는 에폭시 레진과 경화제, 촉매제를 사용하여 다양하게 포뮬레이션을 하였고 DSC (Differential Scanning Calorimeter), TGA (Thermogravimetric Analysis), DEA (Dielectric Analysis) 등의 열분석장비를 이용하여 NCP의 물성과 경화 거동을 확인하였다. 테스트 베드는 면적 $5.2{\times}7.2\;mm^2$, 두께 650 ${\mu}m$, 접속피치 200 ${\mu}m$의 Au범프가 형성된 플립칩 실리콘 다이와 접속패드가 ITO로 finish된 글래스 기판을 사용하였다. 글래스 기판과 실리콘 칩은 본딩 전 PVA Tepla사의 Microwave 플라즈마 장비로 Ar, $O_2$ 플라즈마 처리를 하였으며, Panasonic FCB-3 플립칩 본더를 사용하여 본딩하였다. 본딩 후 접합면의 보이드를 평가하고 die 전단강도로 접합강도를 측정하였다.

• Journal of the Microelectronics and Packaging Society
• /
• v.25 no.4
• /
• pp.155-161
• /
• 2018

A Si chip with the Cu/Au bumps of $100-{\mu}m$ diameter was flip-chip bonded using different anisotropic conductive adhesives (ACAs) onto the local stiffness-variant stretchable substrate consisting of polydimethylsiloxane (PDMS) and flexible printed circuit board (FPCB). The average contact resistances of the flip-chip joints processed with ACAs containing different conductive particles were evaluated and compared. The specimen, which was flip-chip bonded using the ACA with Au-coated polymer balls as conductive particles, exhibited a contact resistance of $43.2m{\Omega}$. The contact resistance of the Si chip, which was flip-chip processed with the ACA containing SnBi solder particles, was measured as $36.2m{\Omega}$, On the contrary, an electric open occurred for the sample bonded using the ACA with Ni particles, which was attributed to the formation of flip-chip joints without any entrapped Ni particles because of the least amount of Ni particles in the ACA.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.41 no.6
• /
• pp.443-453
• /
• 2017

In flip chip technology, the conventional solder bump has been replaced with a copper (Cu) pillar bump owing to its higher input/output (I/O) density, finer pitch, and higher reliability. However, Cu pillar bump technology faces several issues, such as interconnect shorting and higher low-k stress due to stiffer Cu pillar structure when the conventional reflow process is used. Therefore, the thermal compression bonding (TCB) process has been adopted in the flip chip attachment process in order to reduce the package warpage and stress. In this study, we investigated the package warpage induced during the TCB process using a numerical analysis. The warpage of the TCB process was compared with that of the reflow process.

• Electronics and Telecommunications Trends
• /
• v.28 no.5
• /
• pp.100-110
• /
• 2013

플립 칩 본딩 기술은 1960년대에 개발된 기술이지만 가격 경쟁력, 경박단소(輕薄短小)의 부품 구현, 뛰어난 전기적 특성으로 인해 최근에 와서 다시금 주목 받고 있고, 관련 시장이 지속적으로 성장하고 있는 분야이다. 기술 응용 분야로는 스마트 폰, 타블렛 PC 등 개인 휴대 단말기에서 고성능 서버, 게임 컨트롤로 등 다양한 제품을 아우르고 있다. 미세 피치의 경우 관련 시장이 2018년까지 연평균 35%의 폭발적인 성장을 보일 것으로 예측되고 있다. 따라서, 국내외 기업, 연구소, 학계 등에서 활발한 연구 활동이 진행되고 있다. 본고에서는 플립 칩 본딩 기술의 세부 기술을 살펴보며 동시에 피치에 따라 각 세부 기술에 있어 최근에 개발되고 있는 기술 동향을 논의하고자 한다.

• Journal of the Microelectronics and Packaging Society
• /
• v.10 no.2
• /
• pp.27-31
• /
• 2003

RF characteristics of CPW(coplanar waveguide) pattern with bonding pads used in flip-chip packaging of GaAs is studied in the frequency range of 1 GHz to 35 GHz. Simulation, fabrication and evaluation are performed for the proposed patterns. Measurement results show proposed patterns have similar properties of $S_{11}$below -31 dB and $S_{21}$ above -0.19 dB with typical CPW In addition RF properties are improved with the increase of width of ground line. This indicates CPW structure with bonding pads keeps RF characteristics of typical CPW.

• Electronics and Telecommunications Trends
• /
• v.9 no.1
• /
• pp.109-122
• /
• 1994

소자가 고속, 고주파화 되고 ASIC 칩의 개발이 가속화되면서 패키징과 interconnection 의 중요성이 더욱 증대되고 있다. 소자의 성능에 가장 직접적인 영향을 주는 것이 1차 패키징인데 현재 가장 많이 실행되고 있는 것이 wire 등에 의한 본딩 방법이었다. 이러한 기존의 방법은 소자의 고속화와 입출력 숫자의 증가에 따라 점차 그 한계를 보이고 있는데 이에 대한 방안으로는 플립칩 본딩 방식에 의한 패키징을 들 수 있다. 약 20여년 전에 IBM 에서 개발된 이래 많은 발전을 거듭한 이 기술은 최근 기본 기술에 대한 특허권의 소멸과 함께 많은 응용 분야에서 개발이 활발히 진행되고 있다. 따라서 본 고에서는 향후의 가장 유력한 패키징 기술로 인정되고 있는 플립칩 본딩 기술의 특징과 제조 관련 사항을 정리함과 동시에 응용 분야, 특히, OEIC(Optoelectronics Integrated Circuit) 분야에서의 이용 및 개발 현황을 분석, 소개함으로써 이 새로운 패키징 기술에 대한 인식을 제고하고자 한다.

• Journal of the Korean Society for Precision Engineering
• /
• v.25 no.6
• /
• pp.7-12
• /
• 2008

• Journal of the Microelectronics and Packaging Society
• /
• v.24 no.2
• /
• pp.11-15
• /
• 2017

As the heat dissipation problem is increased in 3D multi flip chip packages, an improvement of thermal conductivity in bonding interfaces is required. In this study, the effect of alumina filler addition was investigated in non-conductive paste(NCP). The fine alumina filler having average particles size of 400 nm for the fine pitch interconnection was used. As the alumina filler content was increased from 0 to 60 wt%, the thermal conductivity of the cured product was increased up to 0.654 W/mK at 60 wt%. It was higher value than 0.501 W/mK which was reported for the same amount of silica. It was also found out that the addition of fine sized alumina filler resulted in the smaller decrease in thermal conductivity than the larger sized particles. The viscosity of NCP with alumina addition was increased sharply at the level of 40 wt%. It was due to the increase of the interaction between the filler particles according to the finer particle size. In order to achieve the appropriate viscosity and excellent thermal conductivity with fine alumina fillers, the highly efficient dispersion process was considered to be important.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.2
• /
• pp.37-41
• /
• 2014

One of the important developments in next generation electronic devices is the technology for power delivery and heat dissipation. In this study, the Cu-to-Cu flip chip bonding process was evaluated using the square ABL power bumps and circular I/O bumps. The difference in bump height after Cu electroplating followed by CMP process was about $0.3{\sim}0.5{\mu}m$ and the bump height after Cu electroplating only was about $1.1{\sim}1.4{\mu}m$. Also, the height of ABL bumps was higher than I/O bumps. The degree of Cu bump planarization and Cu bump height uniformity within a die affected significantly on the misalignment and bonding quality of Cu-to-Cu flip chip bonding process. To utilize Cu-to-Cu flip chip bonding with ABL bumps, both bump planarization and within-die bump height control are required.