• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.42 no.3
• /
• pp.237-242
• /
• 2014

Surge phenomenon can be occurred in a compressor when the performance of turbofan engine for an aircraft is changed considerably such as take-off phase. This study is aimed to avoid surge phenomenon. This paper propose the PID and Fuzzy control System for the turbofan engine with control inputs, the VIGV(Variable Inlet Guide Vane) in closed loop, and the fuel mass flow in open loop. We design the Dynamic modeling, NPSS S-function, which is connection block of simulink between NPSS(Engine analysis program) and Simulink. Finally, we certify the performance to prevent a serge phenomenon in the VIGV control system using the both methods, PID and fuzzy.

• Journal of Digital Contents Society
• /
• v.3 no.2
• /
• pp.245-254
• /
• 2002

Currently, communication field for automation system can be divided by simple serial communication for communication between each internal devices and network base remote control system that is based on TCP/IP. In spite of great development of network, communication part for internal control is using simple RS232 base until present. Also, development techniques of system developed by object oriented program in modular programming techniques of each function unit. Currently, it developed by component base development technique that is parts unit of software. This is presented by the new alternative of software development techniques as techniques to composition independent operation unit including business logic and is connected to development of new system. Therefore, this research implemented internal communication Emulate in RS232C based on GUI that apply development techniques of component base. that is, I maked component to commnication control part between receiving and sending and, as composite it, Control part did to handling between send and receive data.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.6
• /
• pp.431-441
• /
• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• 한국신재생에너지학회:학술대회논문집
• /
• 2011.11a
• /
• pp.76.1-76.1
• /
• 2011

석탄 가스화기 내에서 슬래그의 축적에 의한 막힘 현상 등으로 발생 가능한 조업중단을 예방하기 위해 탄의 종류에 따른 슬래그의 유동을 정확히 예측하는 것은 중요하다. 슬래그의 유동은 원료인 석탄의 회 성분 조성 그리고 가스화기 온도의 영향을 크게 받는다. 회가 용융된 형태인 슬래그의 융점 특성을 파악하여 슬래그 거동을 예측하기 위해서는 회를 조성하고 있는 주성분의 비율 뿐 아니라 소량의 성분들도 고려하여야 한다. 또한, 가스화기 조업 조건 중 수증기 분압이 슬래그 점도에 미치는 변화를 파악하여 공정 조건 확립 및 슬래그 계통 제어 로직에 반영 할 수 있다. 따라서, 대표적 열화학 평형계산 프로그램인 Factsage를 이용하여 슬래그 성분의 액상선 온도를 예측해보았다. 슬래그는 회 성분의 조성에 따라 결정 슬래그와 유리 슬래그로 나눌 수 있다. 본 연구에서는 결정 슬래그로는 Alaska Usibelli 탄을, 유리 슬래그로는 Kideco 탄의 조성을 사용하여, 가스화기 조업 조건 중 수증기의 분압에 따라 석탄 슬래그의 형성 및 점도 변화에 직접적인 영향을 미치는 결정 형성에 대한 상관관계를 예측해 보았다. 또한, 슬래그 유동에 영향을 줄 수 있는 요인으로써, 석탄의 품질을 결정하는 인자인 Base/Acid Ratio, Iron in Ash, Calcium in Ash, Silica-to-Alumina Ratio, Inron-to-Calcium Ratio를 달리 변화시켜가며 슬래그 점도 변화에 직접적인 영향을 미치는 결정 형성을 예측하였다. 이 예측결과는 향후 실험 데이터와 비교하여, 슬래그 처리 부분의 모니터링에 기초 자료로 활용될 뿐 아니라, 슬래그점도 측정 시스템의 운전 파라미터를 도출하는데 이용 가능할 것이다.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.30 no.4
• /
• pp.605-616
• /
• 2020

Obfuscation technology delays the analysis of a program by modifying internal logic such as data structure and control flow while maintaining the program's functionality. However, the application of such obfuscation technology to malicious code frequently occurs to reduce the detection rate of malware in antivirus software. The obfuscation technology applied to protect software intellectual property is applied to the malicious code in reverse, which not only lowers the detection rate of the malicious code but also makes it difficult to analyze and thus makes it difficult to identify the functionality of the malicious code. The study of reverse obfuscation techniques that can be closely restored should also continue. This paper analyzes the characteristics of obfuscated code with the option of Pack the Output File and Import Protection among detailed obfuscation technologies provided by VMProtect 3.4.0, a popular tool among commercial obfuscation tools. We present a de-obfuscation algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.12
• /
• pp.2341-2347
• /
• 2016

In this paper, we implement monitoring system for grain sorting using a high-speed FPGA and embedded LINUX. The proposed system is designed by base on web server and web-based applications while existing system was designed by base on stand-alone mode.The interface the Web server with high speed hardware of FPGA is designed on the implemented monitoring system. The proposed system has the advantages of multi-tasking on Linux web server and real-time high speed on FPGA also. The control logic of a high speed rate line-scan CCD camera, the method of center of gravity, HSL decoding and the interface on the Web server are implemented in FPGA. The implemented monitoring system has the advantage of being able to control the grain monitoring, system failure and recovery remotely by web application. As a result, we can upgrade the performance of sorting quality compared by existing system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.8 s.338
• /
• pp.27-34
• /
• 2005

In this paper, FPGA It/w and S/W Embedded system for LDM remote control is implemented. XScale CPU is used on developed system and in communcation ethenet and serial is used. CPU interface with H/W LDM rotation and to drive LDM FPGA logic is implemented, to transmit LDM data from long distance command packet is composed, for S/W Embedded linux is used to design linux device driver and linux application program. This S/W is run by module so by loading this module to linu)( file system it can do any movement. Also by compiling Embedded linux to the system it can lower the price of the system. By using this H/W and S/W theory it can be used on any other embedded system.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.11
• /
• pp.21-30
• /
• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of Advanced Navigation Technology
• /
• v.17 no.5
• /
• pp.560-567
• /
• 2013

In this paper, it is proposed the fault detection method of the ASIC, without the Test Requirement Document(TRD), extracting internal logic circuit and analyzed the function of the ASIC using the multipurpose development program and simulation. If there don't have the TRD, it is impossible to analyze the operation of the circuit and find out the fault detection in any chip. Therefore, we make the TRD based on the analyzed logic data of the ASIC, and diagnose of the ASIC circuit at the gate level through the signal control of I/O pins using the Dynamic Pattern signal. According to the experimental results of the proposed method, we is confirmed the good performance of the fault detection capabilities which applied to the non-memory circuit.

• Journal of Korea Society of Industrial Information Systems
• /
• v.11 no.4
• /
• pp.72-81
• /
• 2006

In this paper, we first define a total of 64 instructions that are considered to be essential and frequently used, construct a datapath diagram, determine the control sequence using a finite state machine, and implement an 8-bit microcontroller using FPGA in VHDL. In the past, only functional simulation results of a rudimentary microcontroller were reported, the microcontroller lacked interrupt handling capability, or it was not implemented in hardware. We have designed a self-contained 8-bit microcontroller such that it can perform data transfer, addition, and logical operations, as well as stack and external interrupt operations. Following timing simulation of the designed microcontroller, we implemented it in an FPGA and verified its operation successfully. The design and implementation has been done under the Altera MAX+PLUS II integrated development environment using the EP1K50TC144-3 chip. The maximum operating frequency, the total number of logic elements used, and the logic utilization were found to be 9.39 MHz, 2813, and 97%, respectively. The result can be used as a microcontroller IP, and as needs arise, the VHDL code can be modified accordingly.