• Journal of Korea Multimedia Society
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• v.10 no.1
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• pp.49-57
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• 2007

Recently, CMOS RF integration has been widely explored in the wireless communication area to save cost, power, and chip area. The direct conversion architecture, rather than a more conventional super-het-erodyne, has been an attractive choice for single-chip integration because of its many advantages. However, the direct conversion architecture has several fundamental problems to solve in achieving performance comparable to a super-heterodyne counterpart. In this paper, we describe a programmable filter for mobile communication terminals using a direct conversion architecture. The proposed filter can be implemented with the active-RC filter and programmed to meet the requirements of different communication standards, including GSM, DECT and WCDMA. The filter can be tuned to select a detail frequency by changing the gate voltage of the MOS resistors. The gain of the proposed architecture can be programmed from 27dB to 72dB using the filter gain and VGA in 3dB steps.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.10
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• pp.74-81
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• 2006

This paper proposes the sensorless vector control scheme of a Non-salient permanent-magnet synchronous motor (SPMSM) using programmable low pass filter (PLPF) to estimate a stator flux with the information of a rotor position and speed. The sesorless vector control of PMSM using PLPF can solves the dc drift problem associated with a pure integrator and a LPF. Also, the PLPF has the phase and gain compensator to estimate exactly rotor position and speed. Therefore, the information of a position and speed is exactly estimated because the drift and offset problems are solved by the PLPF. The experimental results show good performance over the 10[%] of the rated speed and under load condition.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.4
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• pp.184-188
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• 2006

This paper presents DSP based narrow band satellite communication signal power detector for tracking control of mobile satellite antenna system. An analog filter based conventional power detector has poor performance due to frequency drift of carrier. Also, it is very difficult to change an analog filter bandwidth according to changed bandwidth of transmitted signal. To solve these difficulties, we proposed DSP based signal power detector, which is easy to change bandwidth of filter and to match shifted frequency of carrier. The proposed signal power detector consists of a FFT function to measure frequency drift of carrier, a programmable filter bank function to limit of received signal bandwidth and a power calculation function to measure power of filtered signal in 12-bit linear scale. Test results of implemented signal power detector, based on TMS320C5402 DSP, showed that it satisfied required functions and performances and properly operated.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06c
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• pp.361-364
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• 1998

주파수 합성기는 주로 PLL을 이용하여 설계하는데, PLL(Phase-lock loop)이란 출력신호 주파수를 항상 일정하게 유지하도록 구성된 주파수 부귀환 회로로써 기본적인 구성은 위상출력기, 저역통과필터, 전압 제어 발진기로 이루어진다. 이런 PLL의 기본적인 구성에 프로그래머블카운터를 VCO의 출력단에 부가하여 구성한 형태가 주파수합성기이다. 이 주파수합성기의 출력을 프로그래머블 디바이더에 입력하기 전에 주파수를 낮출 필요가 있는데, 현재 슈퍼헤테로다인 다운 컨버터방식과 프리스케일러방식과 펄스 스웰로 카운터를 사용하는 방식 등의 3가지 방법이 있다. 본 논문에서는 펄스 스웰로 카운터 방식의 주파수 합성기를 MATLAB의 GUI환경과 병행하여 시뮬레이션 과정을 통한 동작특성을 이해하고, 한 화면에서 이루어지는 조작에 의해 모든 주파수 합성기의 요소를 관찰할 수 있도록 모델링하였다. 그리고, 모델링한 주파수합성기와 실제 주파수합성기에서 예상되는 출력과 비교하여 그 결과에 있어서 얼마나 유사한지 살펴보았다.

• Journal of Broadcast Engineering
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• v.20 no.5
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• pp.774-777
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• 2015

This paper introduces the world's first programmable video-processing platform for the enhancement of the video quality of the 8K(7680x4320) UHD(Ultra High Definition) TV operating up to 60 frames per second. In order to support required computing capacity and memory bandwidth, the proposed platform implemented several key features such as symmetric multi-cluster architecture for parallel data processing, a ring-data path between the clusters for data pipelining and hardware accelerators for computing filter operations. The proposed platform based on RP(Reconfigurable Processor) processes video quality enhancement algorithms and handles effectively new UHD broadcasting standards and display panels.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.5 no.2
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• pp.96-100
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• 2012

Existing, widely used industrial controller programmable logic controller (PLC) using the high cost and maintenance was a difficult problem. In addition, the network configuration was not easy. Thus, the filter press by remote control and management to improve productivity and shorten maintenance time. Variety of smart devices (smart phones, iPad, tablet PC, etc.) Remote control is possible by utilizing the existing controlled by the PLC addresses maintenance and improved performance compared to that of possible filter press control and management system was developed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.175-184
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• 2006

In this paper, we describe a 900MHz CMOS RF transceiver using an ISM band for ZigBee applications. The architecture of the designed rx front-end, which consists of a low noise amplifier, a down-mixer, a programmable gain amplifier and a band pass filter. And the tx front-end, which consists of a band pass filter, a programmable gain amplifier, an up-mixer and a drive amplifier. A low-if topology is adapted for transceiver architecture, and the total current consumption is reduced by using a low power topology. Entire transceiver is verified by means of post-layout simulation and is implemented in 0.18um RF CMOS technology. The fabricated chip demonstrate the measured results of -92dBm minimum rx input level and 0dBm maximum tx output level. Entire power consumption is 32mW(@1.8VDD). Die area is $2.3mm{\times}2.5mm$ including ESD protection diode pads.

• Proceedings of the KAIS Fall Conference
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• 2011.05a
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• pp.358-361
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• 2011

본 논문에서는 ADSL용 아날로그 Front-end의 수신단과 송신단에 활용하기 위한 저전압 특성의 3V CMOS 프로그램머블 증폭기(PGA)를 설계하였다. 설계된 수신단의 PGA는 1.1MHz로 연속시간 저역통과 필터와 연결하여 0dB에서 30dB까지 이득을 조정해주며, 송신단의 PGA는 138kHz의 저역필터와 연결하여 -15dB에서 0dB까지의 이득을 조정할 수 있다. 모든 PGA의 이득은 디지털 로직과 메인 컨트롤러에 의해서 프로그램될 수 있도록 설계하였다. 설계된 PGA는 $0.35{\mu}m$ CMOS 파라미터를 이용하여 Hspice 시뮬레이션으로 그 특성을 확인하였다.

• Journal of the Korean Institute of Intelligent Systems
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• v.17 no.4
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• pp.477-482
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• 2007

This paper presents an audio decoder architecture which can decode AC-3 and MPEG-2 audio bit-streams efficiently. MPEG-2 synthesis filtering is modified by the 32-point FFT to share the common data path with the AC-3's. A programmable Audio DSP core and a hardwired common synthesis tilter are incorporated for effective decoding of two different formats.

• Journal of Korea Multimedia Society
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• v.5 no.6
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• pp.753-758
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• 2002

In this paper, low voltage 3V CMOS programmable gain amplifier(PGA) for using in the transmitter and receiver of ADSL analog front-end is designed. The designed receive PGA is connected with 1.1MHz continuous lowpass fillet and controls the gain from 0dB to 30dB. And also the transmitter PGA is connected with 138KHz lowpass filter and controls the gain from -15dB to 0dB. The gain of All PGAs can be programmed by digital logic circuits and main controller. The designed PGAs are verified using HSPICE simulation with $0.35\mu{m}$ CMOS parameter.