• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.4
• /
• pp.939-947
• /
• 2010

The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.6
• /
• pp.1107-1114
• /
• 2004

System Packet Interface Level 4 Phase 2(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. SPI-4.2 core consists of Tx and Rx modules and supports full duplex communication. Tx module of SPI-4.2 core writes 64-bit data word and 14-bit header information from the user interface into asynchronous FIFO and transmits DDR(Double Data Rate) data over PL4 interface. Rx module of SPI-4.2 core operates in vice versa. Tx and Rx modules of SPI-4.2 core are designed to support maximum 256-channel and control the bandwidth allocation by configuring the calendar memory. Automatic DIP4 and DIP-2 parity generation and checking are implemented within the designed core. The designed core uses Xilinx ISE 5.li tool and is described in VHDL Language and is simulated by Model_SIM 5.6a. The designed core operates at 720Mbps data rate per line, which provides an aggregate bandwidth of 11.52Gbps. SPI-4.2 interface core is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.9C
• /
• pp.801-809
• /
• 2007

LDPC Low Density Parity Check) code, which is an error correcting code determined to be applied to the 4th generation mobile communication systems, requires a heavy computational complexity due to iterative decodings to achieve a high BER performance. This paper proposes an algorithm to reduce the number of decoding iterations to increase performance of the decoder in decoding latency and power consumption. Measuring changes between the current decoded LLR values and previous ones, the proposed algorithm predicts directions of the value changes. Based on the prediction, the algorithm inverts the sign bits of the LLR values to speed up convergence, which means parity check equation is satisfied. Simulation results show that the number of iterations has been reduced by about 33% without BER performance degradation in the proposed decoder, and the power consumption has also been decreased in proportional to the amount of the reduced decoding iterations.

• Journal of the Institute of Convergence Signal Processing
• /
• v.4 no.4
• /
• pp.73-80
• /
• 2003

In this paper, we propose a ETD-turbo code(Enhanced Time Diversity turbo code) which is a novel turbo code configuration to increase the time diversity effect and analyze the performance of ETD-turbo coded MC-CDMA system. The ETD-turbo code, which is added another interleaver to the conventional turbo code structure, is consisted. Time diversity effect of the ETD-turbo code is improved by every parity bits converted into interleaver pattern. In order to the performance of the ETD-turbo code, we conduct a computer simulation about interleaver type. And we make comparison between the performance of ETD-turbo coded MC-CDMA system and the conventional turbo coded MC-CDMA system. By the simulation results, ETD-turbo code has less BER than the conventional turbo code and time delay is decreased by reducing iteration numbers. Therefore, it is defined that the performance of ETD-turbo coded MC-CDMA system is improved than the conventional turbo coded MC-CDMA system.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2008.11a
• /
• pp.81-84
• /
• 2008

최근 센서네트워크와 같은 에너지 제한 환경을 위한 경량화 부호화 기술의 필요성이 대두됨에 따라 분산 소스 부호화 기술(Distributed Source Coding)의 응용기술로 비디오 부호화 복잡도의 대부분을 차지하는 움직임 예측/보상과정을 부호화기가 아닌 복호화기에서 수행하는 분산 비디오 부호화 기술(Distributed Video Coding)에 대한 연구가 활발히 이루어져 왔다. 이에 가장 대표적인 기술인 Wyner-Ziv 코딩 기술은 채널 코드를 이용하여 원본 프레임과 이에 대한 복호화기의 예측영상인 보조정보 사이의 잡음을 제거하여 영상을 복원한다. 일반적으로 보조정보는 원본영상에 유사한 키 프레임간의 프레임 보간을 통하여 생성되며 채널 코드는 Shannon limit에 근접한 성능을 보이는 Turbo 코드나 LDPC 코드가 사용된다. 이와 같은 채널 코드의 복호화는 채널 잡음 모델에 기반하여 수행되어지며 Wyner-Ziv 코딩 기술에서는 이 채널 잡음 모델을 '상관 잡음 모델' (Correlation Noise Modeling)이라 하고 일반적으로 Laplacian이나 Gaussian으로 모델화 한다. 하지만 복호화기에는 원본 영상에 대한 정보가 없기 때문에 정확한 상관 잡음 모델을 알 수 없으며 잡음 모델에 대한 예측의 부정확성은 잡음 제거를 위한 패리티 비트의 증가를 야기해 부호화 기술의 압축 성능 저하를 가져온다. 이에 본 논문은 원본 프레임과 보조정보 사이의 잡음을 정확하게 예측하여 잡음을 정정할 수 있는 향상된 상관 잡음 모델을 제안한다. 제안 방법은 잘못된 잡음 예측에 의해 Laplacian 계수가 너무 커지는 것을 방지하면서 영상내의 잡음의 유무에 별다른 영향을 받지 않는 새로운 문턱값을 사용한다. 다양한 영상에 대한 제안 방법의 실험 결과는 평균적으로 약 0.35dB에 해당하는 율-왜곡 성능 향상을 보여주었다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.6
• /
• pp.1355-1362
• /
• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• The KIPS Transactions:PartA
• /
• v.11A no.1
• /
• pp.81-88
• /
• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.5
• /
• pp.31-40
• /
• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.3A
• /
• pp.213-220
• /
• 2009

Cooperative diversity is a promising technique for range extension and diversity increase without the use of multiple transmit antennas at the user equipment. In this paper, we propose a cooperative hybrid automatic repeat request relay method with adaptive retransmission to increase the throughput when the SNR of a source user is low. In the proposed method, the source user transmits the first segment of a codeword to relay users and a base station. If the base station fails to recover the information from the received packet, it requests the source or some relay users to retransmit the packet previously sent. In addition, the retransmission type of a selected user is chosen from repetition or incremental redundancy according to the quality of systematic bits in a turbo codeword. Simulation results show that the proposed method improves the throughput compared to conventional methods, and the improvement is significant when the source user has a low SNR.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38A no.9
• /
• pp.750-758
• /
• 2013

In this paper, we introduce the low-density parity-check (LDPC) coded orthogonal frequency division multiplexing (OFDM) subframe reordering scheme for achieving equal combined power allocation in type I hybrid automatic repeat request (H-ARQ) systems and analyze the performance improvement by using the channel capacity. Also, it is confirmed that the layered decoding for subframe reordering scheme in H-ARQ systems gives faster convergence speed. It is verified from numerical analysis that a subframe reordering pattern having larger channel capacity shows better bit error rate (BER) performance. Therefore the subframe reordering pattern achieving equal combined power allocation for each subframe maximizes the channel capacity and outperforms other subframe reordering patterns. Also, it is shown that the subframe reordering scheme for achieving equal combined power allocation gives better performance than the conventional Chase combining scheme without increasing the decoding complexity.