• Proceedings of the Computational Structural Engineering Institute Conference
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• 2010.04a
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• pp.114-117
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• 2010

에너지자원(석유, 천연가스, 전기) 이송과 정보전달(해저광케이블)을 위한 다양한 형태의 해저 매설관이 해저면에 설치되어 운영이 되고 있다. 이들 매설관은 지진 또는 해저사면의 유실과 같은 자연재해로 인해 파괴되는 일들이 빈번하게 발생되고 있다. 그 외 태풍 등에 의해 발생되는 파랑하중에 의해서도 이들 매설관이 종종 파괴되는 일이 발생되기도 한다. 태풍 등에 의한 파랑하중은 해저지반에 과다한 과잉간극수압을 발생시켜 지반 액상화를 유발 세굴을 발생시키는데 이로 인해 매설관 하부에는 과도한 인장응력이 유발되어 매설관의 파괴 문제가 야기된다. 만약 석유수송 해저매설관이 파괴되면 경제적?산업적 측면에서 직접적인 피해 이외에도 해양환경에 미치는 영향은 매우 크다고 볼 수 있다. 따라서 파랑하중에 의한 해저매설관 주변 지반의 거동 분석 및 안정성 평가에 관한 연구가 요구된다.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1623-1626
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• 2002

본 논문에서는 IEEE 802.11a 무선 랜 모뎀에 적용할 파이프 라인구조의 FFT 설계 및 구현에 대해서 제시한다. 구현된 FFT의 기본 구조는 radix-4 Single Delay Format 이나 제안된 나비 연산기에 의해서 복잡도는 radix-2방식과 동일하며 저전력을 고려해서 구현하였다. 구현된 FFT는 $0.35{\mu}m$ LG 라이브러리를 이용하여 합성되었고 64-포인트 FFT/IFFT를 $4{\mu}s$에 수행을 하며 16MHz로 동작을 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.61-68
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• 2008

In this paper, we propose an efficient hardware architecture and algorithm to increase an encoding process rate and implement a hardware for CABAC (Context Adaptive Binary Arithmetic Coding) which is used with one of the entropy coding ways for the latest video compression technique, H.264/AVC (Advanced Video Coding). CABAC typically provides a better high compression performance maximum 15% compared with CAVLC. However, the complexity of operation of CABAC is significantly higher than the CAVLC. Because of complicated data dependency during the encoding process, the complexity of operation is higher. Therefore, various architectures were proposed to reduce an amount of operation. However, they have still latency on account of complicated data dependency. The proposed architecture has two techniques to implement efficient pipeline architecture. The one is quick calculation of 7, 8th bits used to calculate a probability is the first step in Binary arithmetic coding. The other is one step reduced pipeline arcbitecture when the type of the encoded symbols is MPS. By adopting these two techniques, the required processing time was reduced about 27-29% compared with previous architectures. It is designed in a hardware description language and total logic gate count is 19K using 0.18um standard cell library.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.75-82
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• 2000

In this paper, a new low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For the reduction of switched capacitance, the ELM adder of the proposed ALU is inactive while the logical operation is performed and P(propagation) block has a dual bus architecture. A new efficient P and G(generation) blocks are also proposed for the above ALU architecture. ELM adder, double-edge triggered register and the combination of logic style are used for low power consumption as well. As a result of simulations, the proposed architecture shows better power efficient than conventional architecture$^{[1,2]}$ as the number of logic operation to be performed is increased over that of arithmetic to logic operation to be performed is 7 to 3, compared to conventional architecture. The proposed ALU was fabricated with 0.6${\mu}m$ single-poly triple-metal CMOS process. As a result of chip test, the maximum operating frequency is 53MHz and power consumption is 33mW at 50MHz, 3.3V.

• Journal of KIISE
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• v.44 no.6
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• pp.573-580
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• 2017

Despite the recent remarkable advances in the computing power of mobile devices, the heat and battery problems still restrict their performances, particularly compared to PCs. Therefore, in the application of the ray-tracing technique for high-quality rendering, the consideration of a method that traces only the secondary rays while the effects of the primary rays are generated through rasterization-based OpenGL ES rendering is worthwhile. Given that most of the rendering time is for the secondary-ray processing in such a method, a new volume-grid technique for dynamic scenes that enhances the tracing performance of the secondary rays with a low coherence is proposed here. The proposed method attempts to model all of the possible spatial secondary rays in a fixed number of sampling rays, thereby alleviating the visitation problem regarding all of the cells along the ray in a uniform grid. Also, a hybrid rendering pipeline that speeds up the overall rendering performance by exploiting the mobile-device CPU and GPU is presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• The Journal of the Korea Contents Association
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• v.13 no.11
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• pp.523-532
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• 2013

Since conventional methods for the reconstruction of 3D objects used a number of cameras or pictures, they required specific hardwares or they were sensitive to the photography environment with a lot of processing time. In this paper, we propose a 3D object reconstruction method using one photograph based on structured light in ubiquitous environments. We use color pattern of the conventional method for structured light. In this paper, we propose a novel pipeline consisting of various image processing techniques for line pattern extraction and matching, which are very important for the performance of the object reconstruction. And we propose the optimal cost function for the pattern matching. Using our method, it is possible to reconstruct a 3D object with efficient computation and easy setting in ubiquitous or mobile environments, for example, a smartphone with a subminiature projector like Galaxy Beam.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.1
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• pp.9-26
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• 2005

In the pursuit of ever higher levels of performance, recent computer systems have made use of deep pipeline, dynamic scheduling and multi-issue superscalar processor technologies. In this situations, branch prediction schemes are an essential part of modem microarchitectures because the penalty for a branch misprediction increases as pipelines deepen and the number of instructions issued per cycle increases. In this paper, we propose a novel branch prediction scheme, direction-gshare(d-gshare), to improve the prediction accuracy. At first, we model a neural network with the components that possibly affect the branch prediction accuracy, and analyze the variation of their weights based on the neural network information. Then, we newly add the component that has a high weight value to an original gshare scheme. We simulate our branch prediction scheme using Simple Scalar, a powerful event-driven simulator, and analyze the simulation results. Our results show that, compared to bimodal, two-level adaptive and gshare predictor, direction-gshare predictor(d-gshare. 3) outperforms, without additional hardware costs, by up to 4.1% and 1.5% in average for the default mont of embedded direction, and 11.8% in maximum and 3.7% in average for the optimal one.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.12 no.1
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• pp.75-82
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• 1999

일반 해양 구조물이나 해저면에 설치되는 해저 관로는 외력에 의한 변형이 발생된다. 구조물 형상이 복잡하거나, 구성 요소의 개수가 많을 경우 응력해석 시 많은 초기값이 필요하고 해석 시간 또는 장 시간 소요된다. 해양 구조물에 작용하는 대표적인 외력은 파도, 조류, 바람이고 이런 외력은 구조물의 사용 기간(operation life)동안 계속적으로 작용하기 때문에 구조물의 변형율은 항상 허용치 안에서 발생되도록 설계되어야 한다. 허용 변형은 탄성범위 내에 존재해야 하며, 비교적 큰 변형을 일으키는 구조물이나 해저파이프라인의 응력해석을 수치적으로 접근하는 방법을 고찰하였다. 평행상태의 하중 벡터값만 직각 좌표계에서 인트린직(intrinsic) 좌료로 변환시킬 때 변형이 발생함으로, 본 논문에서 소개하는 이차 요소(quadratic element)방법을 사용할 경우 수치해석 시 많은 장점이 있다는 것을 보여준다. 본 방법을 도입함으로써 비교적 큰 변형이 발생되는 구조물 해석 시 일반 수치해석 방법과 그 결과는 같으나 해석 시간을 단축시킬 수 있다는 장점이 있다. 응력 해석 시 국부 강도 행열(element stiffness matrix)은 방향과 무관하며 이차요소 방법을 사용하여 각 요소 벡터를 발생시켰다. 해저관로 일점 상승 시 관로에 작용하는 변형과 상승력에 따른 휨 모멘트를 산출하여 일반적으로 사용되는 선형이론과 비교하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.771-777
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• 2012

This paper proposes a binary arithmetic encoder of CABAC using a Common Operation Unit including the three modes. The binary arithmetic encoder performing arithmetic encoding and renormalizer can be simply implemented into a hardware architecture since the COU is used regardless of the modes. The proposed binary arithmetic encoder of CABAC includes Context RAM, Context Updater, Common Operation Unit and Bit-Gen. The architecture consists of 4-stage pipeline operating one symbol for each clock cycle. The area of proposed binary arithmetic encoder of CABAC is reduced up to 47%, the performance of proposed binary arithmetic encoder of CABAC is 19% higher than the previous architecture.