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http://dx.doi.org/10.6109/jkiice.2012.16.4.771

The Hardware Design of CABAC for High Performance H.264 Encoder  

Myoung, Je-Jin (한밭대학교 정보통신공학과)
Ryoo, Kwang-Ki (한밭대학교 정보통신공학과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.16, no.4, 2012 , pp. 771-777 More about this Journal
Abstract
This paper proposes a binary arithmetic encoder of CABAC using a Common Operation Unit including the three modes. The binary arithmetic encoder performing arithmetic encoding and renormalizer can be simply implemented into a hardware architecture since the COU is used regardless of the modes. The proposed binary arithmetic encoder of CABAC includes Context RAM, Context Updater, Common Operation Unit and Bit-Gen. The architecture consists of 4-stage pipeline operating one symbol for each clock cycle. The area of proposed binary arithmetic encoder of CABAC is reduced up to 47%, the performance of proposed binary arithmetic encoder of CABAC is 19% higher than the previous architecture.
Keywords
H.264/AVC; CABAC; Entropy Coding; Video Coding; Binary Arithmetic Coding;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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