• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.18-21
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• 2009

In the digital system, ROM has a large power-consumption and a speed-bottleneck. According to gradual growth of system speed, ROM is demanded to have low-power consumption and high-speed operation design. The ROM adapted in FFT or FIR filter needs method of sequential accessed addressing. We proposed a reduction method for the number of storage cells in this paper. The number of storage cells which is connected with bi-line is reduced by the proposed method so that the capacitance value of bit-time is reduced. In this case, delay time, and power consumption are reduced. Design result of ROM in this paper using the proposed method could reduce up to 86.3% of storage cell '1' compare with conventional method.

• KIISE Transactions on Computing Practices
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• v.21 no.6
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• pp.418-423
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• 2015

As the development of technology advances at exceptional speed, the functions of wearable devices become more diverse and complicated, and many users find some of the functions difficult to use. In this paper, the main aim is to provide the user with an interface that is more friendly and easier to use. The speech recognition is easy to use and also easy to insert an input order. However, speech recognition is problematic when using on a wearable device that has limited computing power and battery. The wearable device cannot predict when the user will give an order through speech recognition. This means that while speech recognition must always be activated, because of the battery issue, the time taken waiting for the user to give an order is impractical. In order to solve this problem, we use gesture recognition. This paper describes how to use both speech and gesture recognition as a multimodal interface to increase the user's comfort.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.35-40
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• 2012

This paper has proposed a 3~5 GHz IR-UWB low power transmitter for range detection application. Proposed transmitter which has been implemented in a $0.13{\mu}m$ CMOS technology is all digital circuit that consist of simple digital logic. this feature insure low complexity and low power consumption. In addition, center frequency can be changed by adopting voltage controlled delay cell for avoiding existing another radio frequency in UWB low band. Proposed circuit consume only 10pJ/b from 1.2 V supply voltage. The simulation results show 3.3~4.3 GHz center frequency controllability, -51 dBm/MHz maximum output power and is satisfied with FCC regulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.7
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• pp.1001-1008
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• 2018

In this paper, we propose an efficient location tracking scheme using wireless signals for various situations in marine environment that requires location information for many reasons such as lifesaving, accident prevention, and facility management. Our proposed location tracking scheme not only monitors user's location, but also minimizes the risk under the user's limited battery power budget. The position of a user can be obtained at base stations from the strengths of the received signals from the user. In this case, it may require to prevent the user from getting out of the predetermined safe area. For each location in the safe area, we define a risk function, which is influenced by many factors such as location accuracy, depth, flow rate, and geometry. Our proposed scheme is based on finger printing technique and aims at minimizing the average risk of each user in the safe area.

• Journal of the Korea Society of Computer and Information
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• v.14 no.12
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• pp.17-24
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• 2009

More recently, the Green Computing have become a important issue in all fields of industry. The energy efficiency cannot be over-emphasized. Microprocessor companies such as Intel Corporation design processors with taking both energy efficiency and performance into account. Nevertheless, general computer users typically utilize the CPU overclocking to enhance the application performance. The overclocking is traditionally considered as an evil in terms of the power consumption. In this paper, we present effective CPU overclocking schemes, which raise CPU frequency while keeping current CPU supply voltage for energy reduction and performance improvement. The proposed scheme gain both energy reduction and performance improvement. Evaluation results show that our proposed schemes reduce the processor execution time as much as 17% and total computer system energy as much as 5%, respectively. In addition, our effective CPU overclocking schemes reduce the Energy Delay Product (EDP) as much as 22%, on average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.4
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• pp.25-32
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• 2014

Powerline communications (PLC) is a promising medium for network access technology where smart grid aided network services can be provided. In the presence of frequency selective fading in the PLC channel, orthogonal frequency division multiplexing (OFDM) is a technique for reliable communications. This paper presents a spectral efficient method using a superimposed hidden pilot for OFDM-based PLC systems. Based on the scheme using a hidden pilot, it is possible to estimate the channel with no consumption of bandwidth, but with utilization of power allocated to the hidden pilot. Computer simulations showed that the proposed scheme provides higher achievable data rate than that of the conventional schemes in low voltage and medium voltage transmission lines.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.249-255
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• 2007

In general, a large amount of the memory accesses are required for the CAVLC decoding in H.264/AVC. It is a serious problem for the applications such as a DMB and videophone services because the considerable power is consumed for accessing the memory. In order to solve this problem, we propose an efficient decoding method for the coeff-token which is one of the syntax elements of CAVLC. In this paper, the variable length code table is re-designed with the new codewords which are defined by investigating the architecture of the conventional codeword for the coeff_token element. A new coeff_token decoding method is developed based on the suggested table. The simulation results show that the proposed algorithm achieves an approximately 85% memory access saving without video-quality degradation, compared to the conventional CAVLC decoding.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.219-225
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• 2012

A low-power, low-noise pre-amplifier for digital hearing-aid application is designed. This pre-amplifier amplifies single-ended signal from an electret microphone, and produces differential output to be delivered to an ADC. It has a variable gain of 3.6, 7.2, 14.4 and 28.8 with a bandwidth between 100Hz~10kHzon. The measurement results show 85 dB of SNR, 0.05 % of harmonic distortion and $200{\mu}W$ of power consumption with 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.1-6
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• 2009

This paper presents new high speed architecture using DBI(Data Bus Inversion) in DRAM. The DBI is one of the general methods in the signaling circuits to decrease the known problems such as SSO and LSI. Many architectures have been proposed to reduce the number of transitions on the data bus. In this paper, the DBI, the Analog Majority Voter (AMV) circuit, the GIO control circuit and the SSO algorithm are newly proposed. The power consumption can he reduced with the help of direct GIO inversion method and the eye diagram of data can be increased to 40ps. Using proposed DBI scheme can produce almost stable SI of DQs against high speed operation. The DBI is fabricated in 90nm CMOS Technology.