• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.43 no.4 s.310
• /
• pp.39-49
• /
• 2006

This paper proposes an efficient verification environment of PCI Express controller that is the future I/O interface. This verification environment consists of a test vector generator, a test bench, and two abstract memories. We also define the assembler set to generate the verification scenarios. In this paper, we propose the random test environment which consists of a random vector generator, a .simulator part, and a compare engine. This verification methodology is useful to find the special errors which are not detected by the basic-behavioral test and hardware-design test.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.3
• /
• pp.32-40
• /
• 2009

In order to reduce time-to-market, the demand for fast fault diagnosis has been increased. In this paper, a fault dropping technique with fault candidate ordering and test pattern ordering for fast fault diagnosis is proposed. Experimental results using the full-scanned ISCAS 89 benchmark circuits show the efficiency of the fault dropping technique with fault candidate ordering and test pattern ordering.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.7 no.1
• /
• pp.83-91
• /
• 1996

The SPICE circuit analysis program has a limited math capability and, in general, cannot be used for RF and microwave simulation because a complex arithmetic is required to compute S-parameters from node voltages. This paper presents two test bench models that can be used to obtain node voltages proportional to incident, reflected, and transmitted signals. From SPICE computed node voltages, S-parameters are computed using the math capability of the PSPICE post processor, PROBE, as an example for a low-pass filter consisting of transmission line sections. The results of this example are compared with another high frequency circuit analysis program, TOUCHSTONE. The difference between the results of these two programs in magnitude was less than 0.003 and in phase was a few tenths of a degree. By using these test benchs to simulate a filter, RF and microwave analysis can be made with the SPICE, which can be a cost-effective and readily available computational tool for educators and practicing engineers.

• Journal of the Institute of Convergence Signal Processing
• /
• v.15 no.2
• /
• pp.55-63
• /
• 2014

In this paper, we introduce the performance evaluation of data archive system for saving correlation result of Daejeon correlator with high-data rate. Daejeon correlator supports various correlation modes, but the speed of correlation result is affected by correlator according to the integration time in each mode. Maximum data rate of Daejeon correlator is 1.4GB/s in case of C1 mode with 25.6ms integration time. In this research, the performance evaluation of the proposed data archive system is conducted for saving correlation results connected with 4 10GbE optical cable with VCS (VLBI Correlation Subsystem), which is the core system of Daejeon correlator. For the experiments, the data archive system for 2 benders was selected and benchmark test was performed. In this paper, the developed data generation program of VCS correlation result file for benchmark test and evaluation results are described.

• Journal of Advanced Navigation Technology
• /
• v.22 no.2
• /
• pp.57-63
• /
• 2018

In the case of aircraft-launched guided weapons, various interface tests such as MIL-STD-1760 based power source, discrete signal, MUX communication as well as BIT of missile can verify system safety and reliability. The purpose of this case study is to develop a test bench based on MIL-STD-1760E for interoperability testing between aircraft and weapons. We proposed a testing method of the launch sequence based on the defined TIME LINE in the development phase of the missile system from the application of the power of the missile to the targeting, the transfer order, and the missile separation process. Furthermore, it will be a reference model that can maximize the verification scope in the development phase of the air to surface missile system by simulating abnormal situation to the inert missile using the error insertion function.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.10
• /
• pp.3226-3235
• /
• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.2 s.332
• /
• pp.73-82
• /
• 2005

Test data volume and power consumption for scan vectors are two major problems in system-on-a-chip testing. Therefore, this paper proposes a new test data compression/decompression method for low power testing. The method is based on analyzing the factors that influence test parameters: compression ratio, power reduction and hardware overhead. To improve the compression ratio and the power reduction ratio, the proposed method is based on Modified Statistical Coding (MSC), Input Reduction (IR) scheme and the algorithms of reordering scan flip-flops and reordering test pattern sequence in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data, not $T_{diff}$, and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead and lower power consumption than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

• Journal of the Korea Computer Industry Society
• /
• v.6 no.3
• /
• pp.559-566
• /
• 2005

ALTIBASE is the relational main memory DBMS that enables us to develop the high performance and fault tolerant applications. It guarantees the short and predictable execution time as well as the basic functionality of conventional disk-based DBMS. We present the overview of system architecture and the performance analysis with respect to the various design choices. The assorted experiments are performed under the various environments. The results of TPC-H and Wisconsin benchmark tests are described. We illustrate the various performance comparisons under the various index mechanisms, the replication models, the transaction durabilities, and the application structures. A performance study shows the ALTIBASE system can be applied to the wide area of industrial DBMS fields.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.7
• /
• pp.13-20
• /
• 2004

In order to set up the design of micro optical bench, optical coupling efficiencies of two sets of test benches are calculated. Simple linear connections of incoming and outgoing optical fibers with and without ball lenses are designed. Positional errors that are possible in actual fabrication processes we considered in the calculations and their tolerances are determined from -3 ㏈ conditions. For a simple fiber-to-fiber connection, the lateral misalignment should be limited to 2.7 um and tilt error 5.8o. In case of the fiber-to-fiber with ball lens, the working distance between fibers can be extended over 60 um. The optical coupling efficiency depends strongly on the positional errors of ball lenses along the optical axis, and it is also found that the lateral and vertical positional errors should be considered simultaneously in order to keep the high coupling efficiency.

• Journal of the Korea Computer Graphics Society
• /
• v.15 no.4
• /
• pp.1-11
• /
• 2009

In this paper, we present a prism-based mesh culling method to improve effectiveness of continuous collision detection which is a major bottleneck in a simulation using polygonal mesh models. A prism is defined based on two matching triangles between a sequence of times m a polygonal model. In order to detect potential colliding set(PCS) of prism between two polygonal models in a unit time, we apply the visibility test based on the occlusion query to two sets of prisms which are defined from two polygonal models in a unit time. Moreover, we execute the narrow band culling based on SAT(Separating Axis Test) to define potential colliding prism pairs from PCS of prisms extracted as a result of the visibility test. In the SAT, we examine one axis to be perpendicular to a plane which divides a 3D space into two half spaces to include each prism. In the experiments, we applied the proposed culling method to pairs of polygonal models with the different size and compared the number of potential colliding prism pairs with the number of all possible prism pairs of two polygonal models. We also compared effectiveness and performance of the visibility test-based method with those of the SAT-based method as the second narrow band culling. In an experiment using two models to consist of 2916 and 2731 polygons, respectively, we got potential colliding prism pairs with 99 % of culling rate.