• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.93-100
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• 2004

Test scheduling of SoC (System-on-a-chip) is very important because it is one of the prime methods to minimize the testing time under limited power consumption of SoC. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoC is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position in test space to minimize the idling test time of test resources. The efficiency of proposed algorithm is confirmed by experiment using ITC02 benchmarks.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.05a
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• pp.687-690
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• 2008

오늘날 산업계에서 시스템 통합은 IT를 계획하는데 있어서 비용을 줄이고 효율성을 향상 시키기 위한 중요한 방법으로 부각되고 있다. 가상화의 장점은 단일서버에 다중의 운영체제를 통합할 수 있는 환경을 제공해 준다. 그러나 올바른 가상화 기술과 시스템 통합을 위한 가상화 구성방법 선택은 중요한 과제이다. 따라서 이 연구의 목적은 유닉스 시스템 가상화 기술을 설명하고 유닉스시스템 기반 상에서 벤치마킹 테스트 도구를 활용하여 HP 가상화 기술인 nPars, vPars, VM 의 성능을 비교테스트를 하고자 한다.

• The Journal of the Korea Contents Association
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• v.5 no.1
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• pp.229-236
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• 2005

Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.45-54
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• 2002

This paper proposes serial test data compression, a novel DFT scheme for embedded cores in SOC. To reduce test data amounts, share bit compression and fault undetectable fault pattern compression techniques was used. A Circuits using serial test data compression method are derived from a scan DFT method including a test-per-clock technique. For an experiment of the proposed compression method, full scan versions of ISCASS85 and ISCASS89 were used. ATALANTA has been used for ATPG and fault simulation. The amount of test data has been reduced by maximum 98% comparing with original data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.72-84
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• 2000

The test patterns for path delay faults consist of two patterns. So in order to test the delay faults, a new weight generation algorithm that is different from the weight generation algorithm for stuck-at faults must be applied. When deterministic test patterns for weight calculation are used, the deterministic test patterns must be divided into several subsets, so that Hamming distances between patterns are not too long. But this method makes the number of weight sets too large in delay testing, and may generate inaccurate weights. In this pater, we perform fault simulation without pattern partition. Experimental results for ISCAS 89 benchmark circuits prove the effectiveness of the new weight generation algorithm proposed in this paper.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.2
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• pp.201-206
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• 2007

In this paper, we propose the efficient low power test methodology of NoC(Network-on chip) for the test of core-based systems that use this platform. To reduce the power consumption of transferring data through router channel, the scan vectors are partitioned into flits by channel width. The don't cares in unspecified scan vectors are mapped to binary values to minimize the switching rate between flits. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method leads to about 35% reduction in test power.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.833-835
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• 1999

지연 고장 테스트는 디지털 회로의 정확한 동작을 보장하기 위해서 필수적이다. 그러나 순차 회로에는 상태 레지스터들이 존재하기 때문에, 지연 고장을 검출하는 것이 쉽지 않다. 이러한 난점을 해결하기 위해 본 논문에서는 역기능적 지정 방법을 좀 더 효율적으로 적용할 수 있는 테스트 알고리듬을 제안한다. ISCAS89 벤치마크 회로에 대한 실험 결과, 테스트 가능한 경로의 수를 기존의 스캔 기법들에 비해 크게 향상시킬 수 있다는 것을 알 수 있다.

• The Journal of the Korea Contents Association
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• v.21 no.12
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• pp.84-94
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• 2021

Graph databases have been developed to efficiently store and query graph data composed of vertices and edges to express relationships between objects. Since the query types of graph database show very different characteristics from traditional NoSQL databases, benchmarking tools suitable for graph databases to verify the performance of the graph database are needed. In this paper, we propose an efficient graph database benchmarking system that supports diversity in graph inputs and queries. The proposed system utilizes OrientDB to conduct benchmarking for graph databases. In order to support the diversity of input graphs and query graphs, we use LDBC that is an existing graph data generation tool. We demonstrate the feasibility and effectiveness of the proposed scheme through analysis of benchmarking results. As a result of performance evaluation, it has been shown that the proposed system can generate customizable synthetic graph data, and benchmarking can be performed based on the generated graph data.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.145-149
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• 2011

Recently, as the design of a system gets larger and more complex, functional verification method based on system-level becomes more important. The verification of a functional block mainly uses BFM(bus functional model). The larger the burden on functional verification is, the more the importance of configuring a proper verification environment increases rapidly. SystemVerilog unifies hardware design languages and verification languages in the form of extensions to the Veri log HDL. The processing of design description, function simulation and verification using same language has many advantages in system development. In this paper, we design DUT that is composed of AMBA bus and function blocks using SystemVerilog and verify the function of DUT in verification environment using layered testbench. Adaptive FIR filter and Booth's multiplier are chosen as function blocks. We confirm that verification environment can be reused through a minor adaptation of interface to verify functions of other DUT.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.41-50
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• 2005

As the size of circuits becomes larger, the test method needs more test data volume and larger test application time. In order to reduce test data volume and test application time, a new test data compression/decompression method is proposed. The proposed method is based on an XOR network uses don't-care-bits to improve compression ratio during seed vectors generation. After seed vectors are produced seed vectors can be merged using two prefix codes. It only requires 1 clock time for reusing merged seed vectors, so test application time can be reduced tremendously. Experimental results on large ISCAS '89 benchmark circuits prove the efficiency of the proposed method.