• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.3-12
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• 2016

Recently, the study on 5G mobile communication systems using the millimeter-wave frequency band have been actively promoted and the importance of compensation of the nonlinearity of power amplifier caused by the characteristics of millimeter-wave frequency propagation attenuation is increasing. In the paper, we propose a piecewise polynomial model based on subdivision coefficient which are characteristics of power amplifier separated linear section and a non-linear section. In addition, the structure of digital predistortion based on the proposed model and direct learning method are proposed to implement a digital predistortion. To verify the proposed model, digital predistortion based on the proposed model and direct learning method for 60 GHz power amplifier using LTE signal implemented in the FPGA. And the hardware test bench measured performance and complexity. The proposed model achieves 3.3 dB gain over the single polynomial model in terms of the ACLR and reduces 7.5 percent in terms of the complexity.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.5
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• pp.124-133
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• 2003

We propose an application of the Object-Oriented design methodology to develop operational flight program(OFP) for stores management computer(SMC) which manages and controls stores inventory, stores activation, launch for missiles, and release of the conventional weapons. For the development of SMC, a military version of PowerPC 603e is used as a central processing unit board and VxWorks real-time operating system is used. The Tornado software development environment(SDE) and the programming language Ada95 are used for OFP development. We design three layerd in the OFP for the independency of the software modules. An avionics system computer(ASC) simulator and a test bench are developed for the SMC integration test and verification test. And the tests are rigorously and successfully conducted.

• Journal of KIISE:Software and Applications
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• v.34 no.1
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• pp.11-17
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• 2007

One of the popular methods used for pattern classification is the MBR (Memory-Based Reasoning) algorithm. Since it simply computes distances between a test pattern and training patterns or hyperplanes stored in memory, and then assigns the class of the nearest training pattern, it cannot explain how the classification result is obtained. In order to overcome this problem, we propose an incremental teaming algorithm based on RPA (Recursive Partition Averaging) to extract IF-THEN rules that describe regularities inherent in training patterns. But rules generated by RPA eventually show an overfitting phenomenon, because they depend too strongly on the details of given training patterns. Also RPA produces more number of rules than necessary, due to over-partitioning of the pattern space. Consequently, we present the IREA (Incremental Rule Extraction Algorithm) that overcomes overfitting problem by removing useless conditions from rules and reduces the number of rules at the same time. We verify the performance of proposed algorithm using benchmark data sets from UCI Machine Learning Repository.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.4
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• pp.125-128
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• 2014

OpenGL ES(OpenGL for Embedded System) 2.0 is one of the most widely used 3D graphics API(application progrma interface) standard for smart phones and tablet PCs at this time. During programming with this API, they prefer desktop environment rather than the target mobile environment, which has relatively low computing power. Thus, we need to emulate the OpenGL ES 2.0 API on the desktop PCs, where only OpenGL API libraries are available. In this paper, we present technical difficulties and their solutions to emulate OpenGL ES 2.0 on desktop PCs. Our final implementation of OpenGL ES 2.0 emulation library works on desktop PCs and passed over more than 96% of the official CTS(conformance test suites) to prove the correctness of our implementation. Additionally, for the commercially available benchmark programs, our implementation shows equivalent execution speeds to the previous commercial OpenGL ES 2.0 implementations.

• Geophysics and Geophysical Exploration
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• v.26 no.2
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• pp.52-61
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• 2023

The use of ultra-high-resolution (UHR) seismic surveys to preceisly characterize coastal and shallow structures have increased recently. UHR surveys derive a spatial resolution of 3.125 m using a high-frequency source (80 Hz to 1 kHz). A digital streamer system is an essential module for acquiring high-quality UHR seismic data. Localization studies have focused on reducing purchase costs and decreasing maintenance periods. Basic performance verification and application tests of the developed streamer have been successfully carried out; however, a comparative analysis with the existing benchmark model was not conducted. In this study, we characterized data obtained by using a developed streamer and a benchmark model simultaneously. Tamhae 2 and auxiliary equipment of the Korea Institute of Geoscience and Mineral Resources were used to acquire 2D seismic data, which were analyzed from different perspectives. The data obtained using the developed streamer differed in sensitivity from that obtained using benchmark model by frequency band.However, both type of data had a very high level of similarity in the range corresponding to the central frequency band of the seismic source. However, in the low frequency band below 60 Hz, data obtained using the developed streamer showed a lower signal-to-noise ratio than that obtained using the benchmark model.This lower ratio can hinder the quality in data acquisition using low-frequency sound sources such as cluster air guns. Three causes for this difference were, and streamers developed in future will attempt to reflect on these improvements.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.20 no.3
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• pp.353-364
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• 2007

In this paper, a nonlinear finite element analysis program NUCAS, which has been developed for assessment of ultimate pressure capacity and failure mode for nuclear containment building is described. Degenerated shell element with assumed strain method and low-order solid element with enhanced assumed strain method is adapted to microscopic material and elasto-plastic material model, respectively. Finally, the performance of the developed program is tested and demonstrated with several examples. From the numerical tests, the present results show a good agreement with experimental data or other numerical results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.119-126
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• 2007

This paper presents an efficient heuristic algorithm to avoid crosstalk which effects to delay of CMOS digital circuit by downsizing and upsizing of Gate. The proposed algorithm divide into two step, step1 performs downsizing of gate, step2 performs upsizing, so that avoid adjacent aggressor to critical path in series. The proposed algorithm has been verified on LGSynth91 benchmark circuits and Experimental results show an average 8.64% Crosstalk Avoidance effect. This result proved new potential of proposed algorithm.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.10
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• pp.38-45
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• 2004

In this paper, a parallel visualization algorithm is proposed for efficient visualization of the massive data generated from large-scale parallel finite element analysis through investigating the characteristics of parallel rendering methods. The proposed parallel visualization algorithm is designed to be highly compatible with the characteristics of domain-wise computation in parallel finite element analysis by using the sort-last-sparse approach. In the proposed algorithm, the binary tree communication pattern is utilized to reduce the network communication time in image composition routine. Several benchmarking tests are carried out by using the developed in-house software, and the performance of the proposed algorithm is investigated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.43-50
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• 2004

The clock skew is one of the major constraints for high-speed operation of synchronous integrated circuits. In this paper, we propose a hierarchical partitioning based clock network design algorithm called Advanced Clock Tree Generation (ACTG). Especially new effective partitioning and refinement techniques have been developed in which the capacitance and edge length to each sink are considered from the early stage of clock design. Hierarchical structures obtained by parhtioning and refinement are utilized for balanced clock routing. We use zero skew routing in which Elmore delay model is used to estimate the delay. An overlap avoidance routing algorithm for clock tree generation is proposed. Experimental results show significant improvement over conventional methods.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.2
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• pp.146-155
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• 2008

To improve the performance of tiled display system, two parallel tiled display algorithms are proposed by combining the sort-first and the sort-last sorting methods. In the proposed algorithms, the view frustum culling is employed along with the OpenGL display list for the sort-first sorting, and the pre-detection sort-last sparse sorting method is used for sort-last sorting. Through the benchmarking tests, the performances of two proposed algorithms are investigated. Based on the observations, it is suggested how to select an optimal algorithm among the two proposed parallel tiled display algorithms for the given visualization model.