• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.33-38
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• 2017

In this paper, a 4-channel common-cathode VCSEL diode driver array with 3.125 Gb/s per channel operation speed is realized. In order to achieve faster speed of the switching main driver with relatively large transistors, the transmitter array chip consists of a pre-amplifier with active inductor stage and also an input buffer with modified equalizer, which leads to bandwidth extension and reduced current consumption. The utilized VCSEL diode provides inherently 2.2 V forward bias voltage, $50{\Omega}$ resistance, and 850 fF capacitance. In addition, the main driver based upon current steering technique is designed, so that two individual current sources can provide bias currents of 3.0 mA and modulation currents of 3.3 mA to VCSEL diodes. The proposed 4-channel VCSEL driver array has been implemented by using a $0.11-{\mu}m$ CMOS technology, and the chip core occupies the area of $0.15{\times}0.18{\mu}m^2$ and dissipates 22.3 mW per channel.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.3
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• pp.72-77
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• 2017

This paper focuses on the development of a supporting S/W tool for the automated design of an automotive press trim die. To define the die design process based on automation, we analyze the press die design process of the current industry and group repetitive works in the 3D modeling process. The proposed system consists of two modules, namely the template models of the trim steel parts and UI function for their auto-positioning. Four kinds of template models are developed to adapt to various situations and the rules of the interaction formula which are used for checking and correcting the directions of the datum point, datum curve, datum plane are implemented to eliminate errors. The system was developed using CATIA Knowledgeware, CAA(CATIA SDK) and Visual C++, in order for it to function as a plug-in module of CATIA V5, which is one of the major 3D CAD systems in the manufacturing industry. The developed system was tested by applying it to various panels of current automobiles and the results showed that it reduces the time-cost by 74% compared to the traditional method.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.239-244
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• 2013

This paper presents a design of the CMOS LDO regulator with a UVLO protection function for a high speed PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. UVLO block between the power transistor and the power supply is added for a low input protection function. Also, UVLO block showed normal operation with turn-off voltage of 2.7V and turn-on voltage of 4 V in condition of 5 V power supply. Proposed circuit generated fixed 3.3 V from a supply of 5V. From SPICE simulation results using a $1{\mu}m$ high voltage CMOS technology, simulation results were 5.88 mV/V line regulation and 27.5 uV/mA load regulation with load current 0 mA to 200 mA.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.12
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• pp.29-38
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• 2001

Recently, as Internet and its services grow rapidly, IETF(Internet Engineering Task Force) introduced a new switching mechanism, MPLS(Multi-Protocol Label Switching), to solve the problem of the scalability in Internet backbone. In this paper, we implemented the LSR loaded with VC-merging function, which causes LSR's management cost to be significantly reduced. We propose a new VC-merge function which supports differentiated services. In case of network congestion in the output buffer of each core LSR, appling link polices to the output modules of the LSR using the EPD algorithm can prevent the buffer from being overflowed. Simulation was performed for Diffserv by using multiple traffic models and investigated the impact of VC-merge method compared to non VC-merge method. The proposed switch is modeled in VHDL and fabricated using the SAMSUNG $0.5{\mu}m$ SOG process.

• Korean Journal of Optics and Photonics
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• v.15 no.6
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• pp.583-590
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• 2004

The autofocus is one of the important processes in the automated vision inspection or measurements using optical microscopes, because it influences the measuring accuracy. In this paper, we used the confocal microscope configuration based on not a pinhole but a single-mode optical fiber. A single mode fiber has the functions of source and detector by applying the reciprocal scheme. As a result, we acquired a simple system configuration and easy alignment of the optical axis. Also, we embodied a fast autofocus system by acquiring the focus error signal through a source modulation technique. The source modulation technique can effectively reduce physical disturbances compared with objective lens modulation, and it is easily applicable to general optical microscopes. The focus error signal was measured with respect to the modulation amplitude, reflectance of the specimen and inclination angle of the measuring surface. The performance of the proposed autofocus system was verified through autofocusing flat mirror surface. In addition, we confirmed that source modulation rarely degrades the depth resolution by the comparison between the FWHMs of axial response curves.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.4
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• pp.49-55
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• 2020

Recently, companies are growing by introducing rational and optimized technology for all processes, including design. In particular, the emergence of ICT-based cloud platforms has given rise to solutions that are equipped with all the necessary business services in corporations and schools, affecting technical education and corporate growth that have not been experienced thus far. The virtual reality technology and convergence of HMD devices utilizing this platform is a new turning point in corporate development. Therefore, this study tested the VR functions used in design based on 3DEXP and HMD VR devices. Second, design utilization and this issue were examined through a survey based on the experimental data. The results showed that 3DEXP and HMD VR technologies are closely related in terms of design utilization and have demonstrated their mediated effects through statistical analysis. Nevertheless, it is not enough to generalize some engineering students as a result of the study. On the other hand, the introduction of HMD VR technology is one of the pillars of education and the implementation of virtual reality technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.350-357
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• 2005

DSRC provides high speed radio link between Road Side Equipment and On-Board Equipment within the narrow communication area. In this paper, a 5.8 GHz up-conversion mixer for DSRC communication system was designed and fabricated using 0.8 m SiGe HBT process technology and IF/LO/RF matching circuits, IF/LO input balun circuits, and RP output balun circuit were all integrated on chip. The chip size of fabricated mixer was $2.7mm\times1.6mm$ and the measured performance was 3.5 dB conversion gain, -12.5 dBm output IP3, 42 dB LO to If isolation, 38 dB LO to RF isolation, current consumption of 29 mA for 3.0 V supply voltage.

• Journal of IKEEE
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• v.15 no.4
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• pp.330-338
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• 2011

In this paper, a current-mode buck-boost converter using Multiple switching devices is presented. The efficiency of the proposed converter is higher than that of conventional buck-boost converter. In order to improve the power efficiency at the high current level, the proposed converter is controlled with PWM(pulse width modulation) method. The converter has maximum output current 300mA, input voltage 3.3V, output voltage from 700mV to 12V, 1.5MHz oscillation frequency, and maximum efficiency 90%. Moreover, this paper proposes watchdog circuits in order to ensure the reliability and to improve the performance of dc-dc converters. An electrostatic discharge(ESD) protection circuit for deep submicron CMOS technology is presented. The proposed circuit has low triggering voltage using gate-substrate biasing techniques. Simulated result shows that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS(8.2V).

• Journal of IKEEE
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• v.17 no.1
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• pp.77-82
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• 2013

In this paper, dc-dc buck converter controled by the peak current-mode pulse-width-modulation (PWM) presented. Based on the small-signal model, we propose the novel methods of the power stage and the systematic stability designs. To improve the reliability and performance, over-temperature and over-current protection circuits have been designed in the dc-dc converter systems. To prevent electrostatic An electrostatic discharge (ESD) protection circuit is proposed. The proposed dc-dc converter circuit exhibits low triggering voltage by using the gate-substrate biasing techniques. Throughout the circuit simulation, it confirms that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS (8.2V). The circuit simulation is performed by Mathlab and HSPICE programs utilizing the 0.35um BCD (Bipolar-CMOS-DMOS) process parameters.

• The KIPS Transactions:PartC
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• v.9C no.1
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• pp.65-72
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• 2002

In this paper, we implement a high-speed swatch tilth the function for label integration to enhance the expansion of networks using the label space of routers efficiently on MPLS over ATM networks. We propose an appropriate hardware structure to support the VC-merge function and differentiated services simultaneously. In this paper, we use the adaptive congestion control method such as EPD algorithm in carte that there is a possibility of network congestion in output buffers of each core LSR. In addition, we justify the validity of the proposed VC-merge method through simulation and comparison to conventional Non VC-merge methods. The proposed VC-merge capable switch is modeled in VHDL. synthesized, and fabricated using the SAMSUNG 0.5um SOG process.