• Journal of Internet Computing and Services
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• v.5 no.3
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• pp.35-43
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• 2004

In packet switching using multistage interconnection networks (MIN's), it is generally assumed that the packet movements successively propagate from the last stage to the first stage in one network cycle. However, Ding and Bhuyan has shown that the network performance can be significantly improved if the packet movements are confined within each pair of adjacent stages using small clock cycles. In this paper, an analytical model for evaluating the performance of input-buffered MlN's employing this network cycle approach is proposed, The effectiveness of the proposed model is confirmed by comparing results from the simulation as well as from Ding and Bhuyan model.

• The KIPS Transactions:PartC
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• v.16C no.5
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• pp.637-644
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• 2009

A study about performance analysis of synchronization clock using measured clock noises is required. Therefore this paper executed the study for performance analysis of synchronization clock and acquirement of maximum number of network node with various clock states using measured clock noises in NG-SDH networks. Also this paper generated a suitable clock model using measured clock noises, and carried out simulations with various clock states. Through the simulation results, maximum numbers were 80 or more network nodes in normal state, and were below 37 nodes in short-term phase transient(SPT) state, and were 50 or more in long-term phase transient(LPT) state. Accordingly this study showed that maximum numbers to meet ITU-T specification were below 37 network nodes in three clock states. Also this study showed that when SPT or LPT states occur from NE network before DOTS system, synchronization source must change with other stable synchronization source of normal state.

• 한국정보통신설비학회:학술대회논문집
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• 2004.08a
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• pp.254-257
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• 2004

위성신호를 매개로 국가표준에 전국의 모든 노드클럭이 동시에 동기될 수 있는 새로운 형태의 망 동기 클럭 공급 시스템을 제안하였으며 이 방식에 의한 실용화 가능성을 확인하였다. 본 논문에서 새로이 제시하는 방식은 단계적인 물리계층에 의해 동기되던 종래의 방식에 비해 모든 슬레이브 국소들이 동시에 동일한 계위의 품질로 동기 될 수 있는 등의 여러 가지 구조적인 장점을 갖고 있다. 서로 멀리 떨어진 지역에서 같은 위성신호를 동시에 측정하여 얻은 시간차데이터를 활용함으로써 위성을 매개로한 기준클럭과 원격지의 슬레이브클럭과의 위상차를 실시간적으로 측정할 수 있었으며, 컴퓨터 제어에 따라 이들 차이를 보상함으로써 전국의 여러노드에서 멀리 떨어진 기준클럭에 위상동기되는 신개념의 슬레이브 클럭 동기시스템을 설계하고 제작하였다. 이 시스템의 측정결과 $10^{-12}$ 이하의 주파수정확도를 유지하였으며 ITU-T의 권고(G.811)를 충분히 만족하는 MTIE 특성을 보여주었다. 현재 전체적으로 자동화 기능을 갖는 초기모델이 구현되었으며 가까운 시일내에 상용화연구를 통해 디지털 통신망의 동기용 노드클럭으로 사용될 수 있으리라 기대한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.56-63
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• 2015

Not only performance analysis but also power analysis at early design stages is important in designing a system-on-chip. We propose a power modeling based on clock gating enable signals that enables accurate power analysis at a high-level. Power state is defined as combinations of the values of the clock gating enable signals and we can extract the clock gating enable signals to generate the power model automatically. Experimental results show that the average power accuracy is about 96% and the speed gain of power analysis at the high-level power is about 280 times compared to that at the gate-level.

• Journal of Internet Computing and Services
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• v.6 no.4
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• pp.141-147
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• 2005

Ding and Bhuyan, however, has shown that the performance of multistage interconnection networks(MIN's) can be significantly improved if the packet movements are confined within each pair of adjacent stages using small clock cycles. In this paper, an effective model for estimating the performance of multibuffered MIN's employing the approach is proposed. the relative effectiveness of the proposed model is identified compared to the traditional design.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.526-529
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• 2003

This paper presents two strategies to refute clock cycles when using stopping rule in VHDL model verification. The first method is that a semi-random variable is defined and the data that stay in the range of semi-random variable are skipped when stopping rule is running. The second one is to keep the old values of parameters when phases are changed. 12 VHDL models are examined to observe the effectiveness of strategies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.39-45
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• 2003

Design verification of VHDL models is getting difficult and has become a critical and time-consuming process in hardware design. Recent]y the methods using Bayesian estimation and stopping rule have been introduced to verify behavioral models and to reduce clock cycles. This paper presents two strategies to reduce clock cycles when using stopping rule in a VHDL model verification. The first method is that a semi-random variable is defined and the data that stay in the range of semi-random variable are skipped when stopping rule is running. The second one is to keep the old values of parameters when phases of stopping rule are changed. 12 VHDL models are examined to observe the effectiveness of strategies, and the simulation results show that more than about 25% of clock cycles is reduced by using the two proposed strategies with 0.6% losses of branch coverage rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.9A
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• pp.868-877
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• 2006

Sensor network applications need synchronized time to the highest degree such as object tracking, consistent state updates, duplicate detection, and temporal order delivery. In addition, reliability issues and fault tolerance in sophisticated sensor networks have become a critical area of research today. In this paper, we proposed a fault tolerant clock management scheme in sensor networks considering two cases of fault model such as network faults and clock faults. The proposed scheme restricts the propagation of synchronization error when there are clock faults of nodes such as rapid fluctuation, severe changes in drift rate, and so on. In addition, it handles topology changes. Simulation results show that the proposed method has about $1.5{\sim}2.0$ times better performance than TPSN in the presence of faults.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.573-575
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• 2014

클럭 경쟁에서 코어 경쟁으로 전환된 요즘. 병렬 프로그래밍은 중요 하다. 동기화 개체를 사용하면 병목 현상이 발생하며, 1:1 Thread 모델은 자원의 낭비와 문맥전환 비용이 발생한다. Thread 풀 모델은 직렬화에 약점을 가지는게 되는데, 본 논문에서는 다중 개체 대응에 적합한 병렬 프로그래밍 모델을 제시한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12B
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• pp.1037-1041
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• 2004

In this paper we propose a new conceptual slave clock system in which remotely located clock is synchronized to the reference clock by intermediation of the satellite time, show a probability of adoption to real network by experiments. This new proposed method has lots of structural advantages over the existing methods because all of the node clocks can be maintained with the same hierarchical quality. The measurement results show that the accuracy of the experimental slave clock system can be kept within a few parts in 1012 and that the MTIE (Maximum Time Interval Error) meets the ITU-T Recommendation G.811 for the primary reference clock A prototype system having fully automatic operational functions has been realized, and it is expected to be commercially used as a node clock for synchronization in the digital communication network in the near future.