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http://dx.doi.org/10.5573/ieie.2015.52.10.056

High-level Power Modeling of Clock Gated Circuits  

Kim, Jonggyu (Dept. of Computer Engineering, Kwangwoon University)
Yi, Joonhwan (Dept. of Computer Engineering, Kwangwoon University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.52, no.10, 2015 , pp. 56-63 More about this Journal
Abstract
Not only performance analysis but also power analysis at early design stages is important in designing a system-on-chip. We propose a power modeling based on clock gating enable signals that enables accurate power analysis at a high-level. Power state is defined as combinations of the values of the clock gating enable signals and we can extract the clock gating enable signals to generate the power model automatically. Experimental results show that the average power accuracy is about 96% and the speed gain of power analysis at the high-level power is about 280 times compared to that at the gate-level.
Keywords
Clock gating; Automatic power modeling; High-level power analysis; ESL power estimation;
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