• Journal of Korea Society of Industrial Information Systems
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• v.16 no.1
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• pp.1-8
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• 2011

Efficient power management plays a crucial role to strengthen competitiveness in the market of portable mobile commodities. This paper presents a proactive power management technique, called by Energy-Aware Scheduling policY (EASY), to exploit the sleep time information of running applications. Different from previous power management approaches focusing on power conservation in standby mode, the proposed scheme characterizes each application program's operational characteristic in active mode by observing how long the task stays in sleep state of CPU scheduler. Based on the measured sleep time, the proposed EASY speculates an adequate CPU clock frequency according to the current CPU workload and scales the frequency directly to the predicted one. Experimental results show that the proposed scheme reduces the power consumption by 10-30% on average compared to traditional DPM approach, with a minimal impact on the performance overhead.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.56-63
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• 2015

Not only performance analysis but also power analysis at early design stages is important in designing a system-on-chip. We propose a power modeling based on clock gating enable signals that enables accurate power analysis at a high-level. Power state is defined as combinations of the values of the clock gating enable signals and we can extract the clock gating enable signals to generate the power model automatically. Experimental results show that the average power accuracy is about 96% and the speed gain of power analysis at the high-level power is about 280 times compared to that at the gate-level.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.77-84
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• 1998

A voltage controlled chaotic circuit has been designed in integrated circuit and fabricated by using 0.8$\mu\textrm{m}$ single poly CMOS technology. The fabricated chaotic circuit consist of sample and hold circuits, op-amps, nonlinear function generator and two phase clock generator. The test results of the chaotic circuit show that periodic state, quasi-periodic state and chaotic state can be obtained according to the input control voltage with the ${\pm}$2.5V power supply and clock rate of 20kHz. In addition, two dimensional chaotic patterns have been observed by connecting this circuit in parallel or series

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.52-58
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• 2001

This paper describes a TTL-to-CMOS input buffer of an SRAM which dissipates a small operating power dissipation. The input buffer utilizes a transistor structure with latch circuit controlled by a internal activation clock pulse. During the low state of that pulse, input buffer is disabled to eliminate dc current. Otherwise, the input buffer operates normally. Simulation results showed that the power-delay product of the purposed input buffer is reduced by 33.7% per one input.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.2
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• pp.227-236
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• 2017

Quantum-dot cellular automata(QCA) consists of nano-scale cells and demands very low power consumption so that it is one of the alternative technologies that can overcome the limits of scaling CMOS technologies. Various circuits on QCA have been researched until these days, a latch required for counter and state control has been proposed as a component of sequential logic circuits. A latch uses a feedback loop to maintain previous state. In QCA, a latch uses a square structure using 4 clocks for feedback loop. Previous latches have been proposed using many cells and clocks in coplanar. In this paper, in order to eliminate these defects, we propose a SR and D latch using multilayer structure on QCA. Proposed three dimensional loop structure is based on multilayer and consists of 3 layers. Each layer has 2 clock differences between layers in order to reduce interference. The proposed latches are analyzed and compared to previous designs.

• ETRI Journal
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• v.8 no.2
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• pp.100-108
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• 1986

본고에서는 TDX-1의 유지보수 기능으로서 개발된 각 기능별 개요 및 특성에 대하여 기술함으로써 TDX-1의 기능을 이해하거나 타 교환기와의 특성을 비교하는데 도움을 줄수 있도록 하였다. TDX-1의 유지보수 기능은 그 수행대상에 따라 프로세서계와 텔리포니계 유지보수 기능으로 구분된다. 프로세서계의 유지보수 기능에는 시스팀 시동, 프로세서 상태처리, 프로세서 시험, 시스팀 클럭관리와 프로세서 장애처리 기능 등이 있으며 텔리포니계 유지보수 기능에는 시스팀 장애 처리, 네트워크 상태 처리, 네트워크 시험과 시스팀 경보처리 기능 등이 속한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.8
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• pp.1283-1291
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• 2002

In this paper, the PLL driven by the DDFS is designed on the schematic using the Q-logic cell based library and is implemented using FPGA QL32 x16B. The measurement results of the frequency synthesizer switching speed were agreement with a register. The simulated results show that the clock delay was generated after eleven clock and if input is random, It has influence on output DA converter has to be very extensive. Therefore, the DDFS used noise shaper to drive PLL by regular interval for input state. Also the bandwidth of DA converter very extensive, the simulation shows that the variation of small input control word is better than the switching speed of PLL.

• Annual Conference of KIPS
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• 2006.05a
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• pp.893-896
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• 2006

최근의 통신망의 급격한 발전으로 디지털 콘텐츠 분야에서도 고화질/고용량으로 변모하고 있으며, 이러한 환경속에서 콘텐츠의 안전한 보호를 위한 고비도, 고속화 및 고신뢰도 암호 알고리즘의 설계가 요구되고 있다. 본 논문에서 제안된 Threshold clock-controlled LM은 클럭 조절형 암호 알고리즘의 클럭 최대 주기를 최소화시켜 키 수열의 발생 속도를 향상 시켰으며 128비트 키, 128 초기화 백터, 그리고 257 비트의 내부 상태를 가지며, 128-비트의 보안 레벨을 유지함으로써 안전성이 보장되어 고화질/고용량의 디지털 콘텐츠 보호에 적합함을 알 수 있다.

• Annual Conference of KIPS
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• 2004.05a
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• pp.1011-1014
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• 2004

본 논문에서 제안된 Self_Decimated LM-128 키 수열 발생기(Keystream generator)는 2개의 비트 메모리 합산 수열발생기(summation generator)를 갖는 자체 클럭 조절형 키 수열 발생기(stream cipher)이다. Self_Decimated LM-128은 LM 계열에서 제시된 특수한 암호로 128비트 키와 128비트 초기 벡터 그리고 257 비트의 내부 상태를 가지며 128 비트의 보안 레벨을 유지한다. 알려진 보안 분석의 공격에 대비해서 2-비트 메모리를 이용한 합산 수열발생기와 자체 클럭 조절형 키 수열 발생기를 포함한다.