• Journal of Korea Multimedia Society
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• v.10 no.3
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• pp.348-357
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• 2007

One of the major issues in recent researches on wireless sensor networks is to reduce energy consumption of sensor nodes operating with limited battery power, in order to lengthen their lifespan. Among the researches, we are interested in the schemes in which a sensor node periodically turns on and off its radio and requires information on the time when its neighbors will wake up (or turn on). Clock synchronization is essential for wakeup scheduling in such schemes. This paper proposes three methods based on the asynchronous averaging algorithm for clock synchronization in sensor nodes which periodically wake up: (1) a fast clock synchronization method during an initial network construction period, (2) a periodic clock synchronization method for saving energy consumption, and (3) a decision method for switching the operation mode of sensor nodes between the two clock synchronization methods. Through simulation, we analyze maximum clock difference and the number of messages required for clock synchronization.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3A
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• pp.237-246
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• 2007

Clock Synchronization is one of the most basic factors to be considered when we implement an indoor synchronization network for indoor positioning. In this paper, we present a new synchronization algorithm which does not employ time stamps in order to reduce the hardware complexity and data overhead. In addition to that, we describe an algorithm that is designed to compensate the frequency drift giving an serious impact on the synchronization performance. The performance evaluation of the proposed algorithm is achieved by investigating MTIE (Maximum Time Interval Error) values through simulations. In the simulations, the frequency drift values of the practical oscillators are used. From the simulation results, it is investigated that we can achieve the synchronization performance under 10 ns when we use 1 second synchronization interval with 1 ns resolution and TCXOs (Tmperature Compensated Cristal Oscillators) both in the master clock and the slave clock.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.171-177
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• 2006

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.134-139
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• 2004

A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of pre-amplifiers, a nonlinear circuit with diodes, a bandpass filter and a clock amplifier. Before implementing the 40 Gb/s clock recovery circuit, a 10 Gb/s clock recovery circuit has been successfully implemented and tested. With the 40 Gb/s clock recovery circuit, when a 40 Gb/s signal of -10 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -20 dBm output power after passing through the nonlinear circuit. The output signal from the nonlinear circuit passes through a narrow-band filter, and then amplified. The implemented clock recovery circuit is planned to be used for the input of a phase locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.64-74
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• 1999

A new clock skew optimization for clock routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevent the total wire length from increasing. As the clock skew is the major constraint for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization can increase total wire length, therefore clock routing is performed within the given skew bound which can not induce the malfunction. Clock routing under the specified skew bound can decrease total wire length Not only total wire length and delay time minimization algorithm using merging point relocation method but also clock skew reduction algorithm using link-edge insertion technique between two nodes whose delay difference is large is proposed. The proposed algorithm construct a new clock routing topology which is generalized graph model while previous methods uses only tree-structured routing topology. A new cost function is designed in order to select two nodes which constitute link-edge. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance difference is short. Furthermore, routing topology construction and wire sizing algorithm is developed to reduce clock delay. The proposed algorithm is implemented in C programming language. From the experimental results, we can get the delay reduction under the given skew bound.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.7B
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• pp.916-927
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• 2001

본 논문에서는 인터넷 환경에서 멀티미디어의 동기를 맞추어 주기 위하여 가상 클럭(VGC : Virtual Global Clock)을 구성하였고, 가상 클락 기반의 SRTS를 제안하여 미디어 내부 동기(sntra_synchronization)를 이루었다. 8bit/8kHz PCM-sampling 음성 신호에서 320byte를 한 프레임으로 했을 때 각 프레임에 순서 번호를 넣어서 미디어간의 동기(inter_synchronization)를 유지한다. Loop Back 방법을 이용하여 구성한 가상 클럭(VGC)은 통신이 가능한 모든 환경에 적용할 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.10
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• pp.1004-1010
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• 2012

In this paper, we propose the algorithm which considers applying recently proposed clock synchronization techniques with quite high accuracy in a few wireless sensor networks researches to time synchronization algorithm for multi-static radar system and especially overcomes the limitation of previous theory, cannot be applied between nodes in non-line of sight (NLOS). Proposed scheme estimates clock skew and clock offset using recursive robust least M-estimator with information of time stamp observations. And we improve the performance of algorithm by tracking and suppressing the time delays difference caused by NLOS system. Futhermore, this paper derive the mean square error (MSE) to present the performance of the proposed estimator and comparative analysis with previous methods.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1075-1085
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• 2005

The purpose of this paper is to design the architecture for synchronization of MB-OFDM UWB system that is being processed the standardization for Alt-PHY of WPAN(Wireless Personal Area Network) at IEEE802.15.3a and to analyze the implementation loss due to 4 parallel synchronization architecture for design or link margin. First an overview of the MB-OFDM UWB system based on IEEE802.15.3a Alt-PHY standard is described. The effects of non-ideal transmission conditions of the MB-OFDM UWB system including carrier frequency offset and sampling clock offset are analyzed to design a full digital architecture for synchronization. The synchronization architecture using 4-parallel structure is then proposed to consider the VLSI implementation including algorithms for carrier frequency offset and sampling clock offset to minimize the effects of synchronization errors. The overall performance degradation due to the proposed synchronization architecture is simulated to be with maximum 3.08 dB of the ideal receiver in maximum carrier frequency offset and sampling clock offset tolerance fir MB-OFDM UWB system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.