• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.684-690
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• 2010

Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.

• Proceedings of the KAIS Fall Conference
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• 2009.05a
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• pp.255-258
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• 2009

최근 EDA 툴의 기술적인 향상과 반도체 공정의 발달로 IC 설계자들은 RISC 프로세서, DSP 프로세서, 메모리 등 많은 IP가 하나로 집적되는 SoC구조가 가능해졌다. 하지만 기존에 사용되는 대부분의 SoC는 공유버스 구조를 가지고 있어, 병목현상이 발생하는 문제점을 가진다. 이러한 문제점은 SoC 내부의 IP들이 많을수록 SoC 플랫폼의 전체 성능이 저하되어, CPU 자체의 속도보다는 효율적인 통신에 의해 성능이 좌우된다. 본 논문에서는 공유버스의 단점인 병목현상을 줄이고 성능을 향상시키기 위하여 크로스바 스위치버스 구조를 제안한다. OpenRISC 프로세서, VGA/LCD 제어기, AC97 제어기, 디버그 인터페이스, 메모리 인터페이스로 구성되는 SoC 플랫폼의 WISHBONE 온칩 공유버스 구조와 크로스바 스위치 버스 구조의 성능을 비교한 결과, 기존의 공유버스보다 26.58%의 성능이 향상됨을 확인하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.166-173
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• 2013

As the number of IPs and the communication volume among them have constantly increased, on-chip crossbar network is now the most widely-used on-chip communication backbone of contemporary SoCs. The on-chip crossbar network consists of multiple crossbars and the connections among the IPs and the crossbars. As the complexity of SoCs increases, it has also become more and more complex to determine the topology of the crossbar network. To tackle this problem, this paper proposes an on-chip crossbar network topology method for application-specific systems. The proposed method uses mixed integer linear programming to solve the topology synthesis problem, thus the global optimality is guaranteed. Unlike the previous MILP-based methods which represent the topology with adjacency matrixes of IPs and crossbar switches, the proposed method uses the communication edges among IPs as the basic element of the representation. The experimental results show that the proposed MILP formulation outperforms the previous one by improving the synthesis speed by 77.1 times on average, for 4 realistic benchmarks.

• Journal of KIISE:Information Networking
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• v.34 no.3
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• pp.203-217
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• 2007

In this paper, a performance evaluation model of Networks with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the switch networks. The characteristic of a network with crossbar switches is determined by both the connection pattern of the switches and the limitation of data flow in a each switch. In this thesis, the evaluation models of three different networks : Multistage interconnection network, Fat-tree network, and other ordinary communication network are developed. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. Two important parameters of the network performance, throughput and delay, are evaluated. The proposed model takes simple and primitive switch networks, i.e., no flow control and drop packet, to demonstrate analysis procedures clearly. It, however, can not only be applied to any other complicate modern switch networks that have intelligent flow control but also estimate the performance of any size networks with multiple-buffered switches. To validate the proposed analysis model, the simulation is carried out on the various sizes of networks that uses the multiple buffered crossbar switches. It is shown that both the analysis and the simulation results match closely. It is also observed that the increasing rate of Normalized Throughput is reduced and the Network Delay is getting bigger as the buffer size increased.

• The KIPS Transactions:PartC
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• v.12C no.1 s.97
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• pp.83-96
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• 2005

The multichannel switch is an architecture widely used for ATM (Asynchronous Transfer Mode). It is known that the fault tolerant characteristic can be incorporated into the multichannel crossbar switching fabric. For example, if a link belonging to a multichannel group fails, the remaining links can assume responsibility for some of the traffic on the failed link. On the other hand, if a fault occurs in a switching element, it can lead to erroneous routing and sequencing in the multichannel switch. We investigate several fault localization algorithm in multichannel crossbar ATM switches with a view to early fault recovery. The optimal algorithm gives the best performance in terms of time to localization but it is computationally complex which makes it difficult to implement. We develop an on-line algorithm which is computationally more efficient than the optimal one. We evaluate its performance through simulation. The simulation results show that the Performance of the on-line algorithm is only slightly sub-optimal for both random and bursty traffic. There are cases where the proposed on-line algorithm cannot pinpoint down to a single fault. We enumerate those cases and investigate the causes. Finally, a fault recovery algorithm is described which utilizes the information provided by the fault localization algorithm The fault recovery algorithm providesadditionalrowsandcolumnstoallowcellstodetourthefaultyelement.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.630-632
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• 1998

본 논문에서는, Multi[le-Buffered a$\times$a Crossbar 수위치의 성능 분석 모형을 제안하고 스위치에 장착된 buffer 의 개수의 중가에 다른 성능 향상 추이를 분석하였다. buffered스위치 기법은 다수 데이터 패킷을 동시에 전송할 때 네트웍에서 발생되는 충돌문제를 효과적으로 해결할 수 있는 방법으로 널리 알려져있다. 제안된 성능 예측 모형은 스위치 입력 단에 유입되는 데이터 패킷이 buffered 스위치 내부에서 전송되는 유형을 확률적으로 분석하여 수립되었다. 모형의 수학적 복잡도 해결을 위하여 확률 식 유도 과정 등에 steady state 개념을 도입하였다. 제안한 모형은 스위치 크기 및 스위치에 장착된 buffer의 개수와 무관하게 buffered a$\times$a 크로스바 스위치의 성능 예측을 가능케 하고, 나아가서 이들로 구성된 다층 연결 망의 성능 분석에 확대 적용이 가능하다. 제안한 수학적 성능 분석 연구는 실효성 검증을 위하여 병행된 시뮬레이션 결과는 미세한 오차 범위 내에서 모형의 예측 데이터와 일치하는 결과를 보여 분석 모형의 타당성을 입증하였다. 또한, 분석 결과 스위치에 소수의 버퍼를 장착했을 때, throughput이 크게 증가하지만, 네 개 이상의 버퍼를 장착되는 버퍼의 개수가 네 개 정도일 경우 가격 대 성능비가 우수한 것으로 추론되었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.291-294
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• 2004

In this paper, we consider the broadcast switch architecture for hish performance multicast packet switching. In input and output buffered switch, we propose a new switch architecture which supports high throughput in broadcast packet switching with switch planes of single input and multiple output crossbars. The proposed switch architecture has a central arbiter that arbitrates requests from plural input ports and generates multiple grant signals to multiple output ports in a packet transmission slot. It provides high speed pipelined arbitration and large scale switching capacity.

• Journal of KIISE:Information Networking
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• v.32 no.2
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• pp.244-253
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• 2005

In this paper, a performance evaluation model of the switch router with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the crossbar switch. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. The performance of the multiple-buffered crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a network that uses the multiple buffered crossbar switches. Less than $2\%$ differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.303-306
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• 2000

In this paper, we propose VC merge capable hardware architecture for scalability based on ATM switching fabric. We implemented a scheduler for configuring crossbars in input-queued switches which support virtual output queues at the input ports. Also, we implemented VC merge capable scheduler at the output ports. We verified the proposed model by using C language, and designed with VHDL language. Then, we simulated and synthesized it with software of the SYNOPSYS corporation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.394-397
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• 2003

In this paper, we describe the implementation of high performance buffer manager that is used in an advanced input-queued switch fabric. The designed buffer manager provides wire-speed cell/packet routing with low cost and tolerates the transmission pipeline latency of request and grant data. The buffer manager is implemented in a FPGA chip and supports the speed of OC-48c, 2.5Gbps per port.