• Journal of the Institute of Electronics Engineers of Korea SC
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• 제40권1호
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• pp.19-29
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• 2003

This paper proposes a CMOS readout circuit for uncooled micro-bolometer arrays adopting a four-point step calibration technique. The proposed readout circuit employing an 11b analog-to-digital converter (ADC), a 7b digital-to-analog converter (DAC), and an automatic gain control circuit (AGC) extracts minute infrared (IR) signals from the large output signals of uncooled micro-bolometer arrays including DC bias currents, inter-pixel process variations, and self-heating effects. Die area and Power consumption of the ADC are minimized with merged-capacitor switching (MCS) technique adopted. The current mirror with high linearity is proposed at the output stage of the DAC to calibrate inter-pixel process variations and self-heating effects. The prototype is fabricated on a double-poly double-metal 1.2 um CMOS process and the measured power consumption is 110 ㎽ from a 4.5 V supply. The measured differential nonlinearity (DNL) and integrat nonlinearity (INL) of the 11b ADC show $\pm$0.9 LSB and $\pm$1.8 LSB, while the DNL and INL of the 7b DAC show $\pm$0.1 LSB and $\pm$0.1 LSB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제18권10호
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• pp.1126-1135
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• 2007

This paper presents the varactor-tuned miniaturized hairpin tunable filter with a single control voltage. The previously proposed miniaturization method is a very straight-forward method to miniaturize a parallel coupled-line filter. In this paper, the miniaturized hairpin tunable filter is proposed with the constant ratio rule of that the capacitances of the each stage always have constant ratio without any dependency to miniaturized electrical length. To show the validity of the proposed method, a 3rd order 0.5 dB ripple Chebyshev fitter with a center frequency of 900 MHz and a fractional bandwidth(FBW) of 10 % was designed and fabricated. The fabricated filter was based on CER-10 substrate of Taconic Inc. with 1SV277 varactor diode of Toshiba Inc. The center frequency of the fabricated filter can be changed from 606 MHz to 944 MHz, 338 MHz with the control voltage from 0.5 V to 4 V. The insertion loss of the proposed filter is increased with the increment of the control voltage, and the filter characteristics are well reserved expect of slight change of the bandwidth with the various control voltage.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• 제16권5호
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• pp.197-203
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• 2016

In this paper, the dipole antenna that can control a beam steering were designed for attaching on LEO(Low Earth Orbit) small satellite. The proposed antenna was based on Yagi-Uda antenna. The parasitic element was proposed as a T-shape. Depending on the state of open or short at the end of a vertical element, we can choose a characteristic of the parasitic element with fixing a vertical element length of the parasitic element. Using this characteristic, we designed the director element and reflector element. The proposed antenna was designed to receive UHF 436.5 MHz. Antenna gain was chosen by link budget between one satellite and the other satellite or between the satellite and the ground station. By changing a vertical element length which is the largest variable that chooses an antenna characteristic, we confirmed that ${\lambda}/2$ length transformer has a result that improve 0.5 dB in comparison ${\lambda}/4$ length transformer from maximum gain direction. In production, we made an on/off switch composed of a diode, capacitor, and inductor control an open and short at the end of the parasitic element. As a result, the gain of antenna used in a link between one satellite and the other satellite had average 5.92 dBi. And the gain of antenna used in a link between the satellite and the ground station had average 0.99 dBi.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제49권1호
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• pp.15-24
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• 2012

In this paper, we suggest the dynamic-response-free SMPS using a new high-resolution DPWM generator based on switched-capacitor delay technique. In the proposed system, duty ratio of DPWM is controlled by voltage slope of an internal capacitor using switched-capacitor delay technique. In the proposed circuit, it is possible to track output voltage by controlling current of the internal capacitor of the DPWM generator through comparison between the feedback voltage and the reference voltage. Therefore the proposed circuit is not restricted by the dynamic-response characteristic which is a problem in the existing SMPS using the closed-loop control method. In addition, it has great advantage that ringing phenomenon due to overshoot/undershoot does not appear on output voltage. The proposed circuit can operate at switching frequencies of 1MHz~10MHz using internal operating frequency of 100 MHz. The maximum current of the core circuit is 2.7 mA and the total current of the entire circuit including output buffer is 15 mA at the switching frequency of 10 MHz. The proposed circuit has DPWM duty ratio resolution of 0.125 %. It can accommodate load current up to 1 A. The maximum ripple of output voltage is 8 mV. To verify operation of the proposed circuit, we carried out simulation with Dongbu Hitek BCD $0.35{\mu}m$ technology parameter.

• Applied Chemistry for Engineering
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• 제28권6호
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• pp.638-644
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• 2017

Pitch based activated carbon fibers for electric double layer capacitor (EDLC) electrodes were treated by oxyfluorination via varying the ratio of fluorine and oxygen gases to improve high power property. As the partial pressure of fluorine increased, the oxyfluorinated activated carbon fibers showed an increase of linear fluorine functional groups. While the oxygen functional groups increased, no changes was observed with respect to the partial gas pressure. The specific surface area and pore volume decreased due to the etching reaction on the activated carbon fiber surface through oxyfluorination, but the mesopore volume increased about 4.5 times. In the case of activated carbon fibers treated with 50% of the fluorine gas partial pressure, the specific capacitance increased to about 29% and 61% at scan rates of 5 and 50 mV/s, respectively. The improvement of the specific capacitance was believed to be due to the introduction of oxygen and fluorine functional groups on the activated carbon fiber surface and the increase of mesopores through oxyfluorination.

• Proceedings of the Korean Vacuum Society Conference
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• 한국진공학회 1999년도 제17회 학술발표회 논문개요집
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• pp.151-151
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• 1999

금속-산화막-반도체(MOS) 소자를 이용하는 집적회로의 발전은 게이트 금속의 규격 감소를 필요로 한다. 규격감소에 따른 저항 증가가 중요한 문제점으로 대두되었으며, 그동안 여러 연구자들에 의하여 금속 게이트에 관련된 연구가 진행되어 왔다. 특히 저항이 낮으며 녹는점이 매우 높은 내화성금속(refractory metal)인 텅스텐(tungsten, W)이 차세대 MOS 소자의 유력한 대체 게이트 금속으로 제안되었다. 텅스텐은 스퍼터링(sputtering)과 화학기상 증착(CVD) 방식을 이용하여 성장시킬 수 있다. 스퍼터링에 의한 텅스텐 증착은 산화막과의 접착성은 우수한 반면에 증착과정 동안에 게이트 산화막(SiO2)에 손상을 주어 게이트 산화막의 특성을 열화시킬 수 있다. 반면, 화학기상 증차에 의한 텅스텐 성장은 스퍼터링보다 증착막의 저항이 상대적으로 낮으나 산화막과의 접착성이 좋지 않은 문제를 해결하여야 한다. 본 연구에서는 감압 화학기상 증착(LPCVD)방식을 이용하여 텅스텐 게이트 금속을 100~150$\AA$ 두께의 게이트 산화막(SiO2 또는 N2O 질화막)위에 증착하여 물리 및 전기적 특성을 분석하였다. 물리적 분석을 위하여 XRD, SEM 및 저항등이 증착 조건에 따라서 측정되었으며, 텅스텐 게이트로 구성된 MOS 캐패시터를 제작하여 절연 파괴 강도, 전하 포획 메커니즘 등과 같은 전기적 특성 분석을 실시하였다. 특히 텅스텐의 접착성을 증착조건의 변화에 따라서 분석하였다. 텅스텐 박막의 SiO2와의 접착성은 스카치 테이프 테스트를 실시하여 조사되었고, 증착시의 기판의 온도에 민감하게 반응하는 것을 알 수 있었다. 또한, 40$0^{\circ}C$ 이상에서 안정한 것을 볼 수 있었다. 텅스텐 박막은 $\alpha$ 및 $\beta$-W 구조를 가질 수 있으나 본 연구에서 성장된 텅스텐은 $\alpha$-W 구조를 가지는 것을 XRD 측정으로 확인하였다. 성장된 텅스텐 박막의 저항은 구조에 따라서 변화되는 것으로 알려져 있다. 증착조건에 따른 저항의 변화는 SiH4 대 WF6의 가스비, 증착온도에 따라서 변화하였다. 특히 온도가 40$0^{\circ}C$ 이상, SiH4/WF6의 비가 0.2일 경우 텅스텐을 증착시킨 후에 열처리를 거치지 않은 경우에도 기존에 발표된 저항률인 10$\mu$$\Omega$.cm 대의 값을 얻을 수 있었다. 본 연구를 통하여 산화막과의 접착성 문제를 해결하고 낮은 저항을 얻을 수 있었으나, 텅스텐 박막의 성장과정에 의한 게이트 산화막의 열화는 심각학 문제를 야기하였다. 즉, LPCVD 과정에서 발생한 불소 또는 불소 화합물이 게이트의 산화막에 결함을 발생시킴을 확인하였다. 향후, 불소에 의한 게이트 산화막의 열화를 최소화시킬 수 있는 공정 조건의 최저고하 또는 대체게이트 산화막이 적용될 경우, 개발된 연구 결과를 산업체로 이전할 수 있는 가능성이 높을 것을 기대된다.

• Journal of the Microelectronics and Packaging Society
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• 제10권2호
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• pp.7-12
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• 2003

The $Bi_{3.3}La_{0.7}O_{12}$(BLT) capacitors with Metal-Ferroelectric-Insulator-Silicon structure were prepared on $SiO_2/Si$ substrates by using sol-gel method. The BLT thin films annealed at $650^{\circ}C$ and $700^{\circ}C$ showed randomly oriented perovskite crystalline structures. The full with at half maximum (FWHM) of the (117) main peak was decreased from $0.65^{\circ}$ to $0.53^{\circ}$ with increasing the annealing temperature from $650^{\circ}C$ to $700^{\circ}C$, indicating the improvement in the crystalline quality of the film. In addition, the grain size and $R_rms$ , values were increased with increasing the annealing temperatures, showing the rough film surface at higher annealing temperatures. From the capacitance-voltage (C-V) measurements, the memory window voltage of the BLT film annealed at $700^{\circ}C$ was found to be about 0.7 V at an applied voltage of 5 V. The leakage current density of the BLT film annealed at $700^{\circ}C$ was about $3.1{\times}10^{-8}A/cm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제38권10호
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• pp.712-720
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• 2001

Algorithms from the research of the layout migration were proposed in the paper. These are automatic recognition algorithm for the VLSI devices from it, graph based construction algorithm to maintain the constraints, dependencies, and design rule between the devices, and high speed compaction algorithm to reduce size of the VLSI area and reuse the design with compacted size for the new technology. Also, this paper describes that why proposed algorithms are essential for the era of the SoC (System on a Chip), design reuse, and IP DB, which are the big concerns in these days. In addition to introduce our algorithms, the benchmark showed that our performance is superior by 27 times faster than that of the commercial one, and has better efficiency by 3 times in disk usage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제45권5호
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• pp.12-18
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• 2008

Ag paste was employed for source and drain electrode of OTFTs and for the data metal lines of OTFT-OLED array on PC(polycarbonate) substrate. We tested two kinds of Ag-pastes such as pastes for 325 mesh and 500 mesh screen mask to examine the pattern ability and electrical performance for OTFTs. The minimum feature size was 60 ${\mu}m$ for 325 mesh screen mask and 40 ${\mu}m$ for 500 mesh screen mask. The conductivity was 60 $m{\Omega}/\square$ for 325 mesh and 133.1 $m{\Omega}/\square$ for 500 mesh. For the OTFT performance the mobility was 0.35 $cm^2/V{\cdot}sec$ and 0.12 $cm^2/V{\cdot}sec$, threshold voltage was -4.7 V and 0.9 V, respectively, and on/off current ratio was ${\sim}10^5$, for both screen masks. We applied the 500 mash Ag paste to OTFT-OLED array because of its good patterning property. The pixel was composed of two OTFTs and one capacitor and one OLED in the area of $2mm{\times}2mm$. The panel successfully worked in active mode operation even though there were a few bad pixels.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제45권5호
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.