• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.9
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• pp.1-5
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• 1999

In this paper, we proposed a novel branch-line coupler using filp-chip technology. The proposed coupler consists of CPW and inverted microstrip. The CPW is on the GaAs flip-chip substrate, and the inverted microstrip is on the alumina main substrate. The ground plane of the CPW is used as a ground plane of the inverted microstrip. And both the transmission lines are connected by solder bump with each other. The characteristics of thisstructure was calculated by FDTD method. The S21, S31 are -3dB and the phase difference is $90^{\circ}$. The calculated characteristics are the same as those of the regular branch-line coupler. This structure can be applied for various kinds of devices using flipchip technology.

• Journal of the Korean Institute of Intelligent Systems
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• v.23 no.4
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• pp.286-291
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• 2013

In this paper, in-line type flip chip bump 3D inspection equipment, using white light interferometer with large F.O.V., which is aimed to be used in flip chip bump test process is developed. Results of flip chip bump height measurement in many substrates and repeatability test results for the bumps in fixed location of each substrate are shown. Test results from test bench and those from developed flip chip bump 3D inspection equipment are compared and as a result repeatability is improved by reducing the impact of system vibration. A valuation basis for the testing quality of flip chip bump 3D inspection equipment is proposed.

• Proceedings of the KAIS Fall Conference
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• 2009.05a
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• pp.372-375
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• 2009

반도체 봉지재란 실리콘 칩, 골드와이어, 리드프레임 등의 반도체 소지를 열, 수분, 충격으로부터 보호하기 위해 밀봉하는 재료로서 EMC(Epoxy Moding Compound)가 가장 많이 쓰인다. EMC는 기계적, 전기적 성능향상을 위한 무기재료로 실리카(Silica), 열에 의해 경화되어 3차원 경화구조를 형성하는 에폭시수지, 빠른 경화특성을 부여하기 위한 경화제로서의 페놀수지, 유기재료와 무기재료 사이의 결합력을 높이기 위해 커플링제, 카본블랙, 이형성 확보를 위한 왁스(Wax), 착색제(Colorant), 난연제(Flame Retardant)등의 첨가제로 구성되는 복합소재로써 본 연구에서는 에폭시의 유형에 따른 용융 실리카를 주충진재로 하여 각각의 봉지재의 첨가제를 기준으로 할 때 다양한 형태의 친환경 비할로겐계 반응형 난연제를 합성하는 기술을 개발하고 비 할로겐계 및 Sb 계 첨가형 난연제의 혼용 배합을 통해 친환경 EMC용 난연제의 제조기술을 개발하였다. 이들 EMC의 요구특성은 요구특성은 외부환경으로부터 칩 보호, 칩을 전기적으로 절연특성 유지, 칩의 작동시 발생되는 열의 효과적인 방출 특성 유지, 실장(Board Mounting)의 간편성 특성을 확보해야 하는 특성을 지니고 있어 이들 요구특성에 적합한 특성조사가 함께 이루어졌다.

• The KIPS Transactions:PartA
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• v.14A no.7
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• pp.391-398
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• 2007

In this paper, we design a future mobile camera standard interface based on the MIPI CSI-2 and D-PHY specification. The proposed CSI-2 have the efficient multi-lane management layer, which the independent buffer on the each lane are merged into single buffer. This scheme can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. The proposed CSI-2 & D-PHY are verified under test bench. We make an experiment on CSI-2 & D-PHY with FPGA type test-bed and implement them onto a mobile handset. The proposed CSI-2 & D-PHY module are used as both the bridge type and the future camera processor IP for SoC.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.6
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• pp.567-574
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• 2003

It is important to design and evaluate the chip waveform with the minimum MAI under the bandwidth constraint in the interference-limited DS-CDMA system. In this paper, by approximation we present the analytical chip waveforms that are proposed and optimized in the reference. Their performances are compared with performances of three conventional chip waveforms: rectangular, half-sine and raised-cosine. Waveform 1 of the proposed chip waveform outperforms the conventional ones. BER and throughput performance are evaluated in the Rayleigh and Nakagami-m fading channels when DPSK modulation is used. When the required BER is 10$\^$-3/ in two fading channels, the capacity of the waveform 1 is improved about 20 % rather than raised-cosine one. When the offered traffic is 30 and the number of packet per bit(N$\sub$d/) is 14, maximum throughput of the waveform 1 is better than raised-cosine chip waveform about 18 % in two fading channels.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.43-51
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• 2014

In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

• KSBB Journal
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• v.24 no.5
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• pp.432-438
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• 2009

Here, we demonstrated simple nucleic acid, RNA, concentration method using polymer micro chip containing glass bead ($100\;{\mu}m$). Polymer micro chip was fabricated by PDMS ($1.5\;cm\;{\times}\;1.5\;cm$, $100\;{\mu}m$ in the height) including pillar structure ($160\;{\mu}m\;(I)\;{\times}\;80\;{\mu}m\;(w)\;{\times}\;100\;{\mu}m\;(h)$, gap size $50\;{\mu}m$) for blocking micro bead. RNA could be adsorbed on micro glass bead at low pH by hydrogen bonding whereas RNA was released at high pH by electrostatic force between silica surface and RNA. Amount of glass beads and flow rate were optimized in aspects of adsorption and desorption of RNA. Adsorption and desorption rate was measured with real time PCR. This concentrated RNA was applied to amplification micro chip in which NASBA (Nucleic Acid Sequence Based Amplification) was performed. As a result, E.coli O157 : H7 in the concentration of 10 c.f.u./10 mL was successfully detected by these serial processes (concentration and amplification) with polymer micro chips. It implies this simple concentration method using polymer micro chip can be directly applied to ultra sensitive method to measure viable bacteria and virus in clinical samples as well as environmental samples.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4A
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• pp.408-416
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• 2010

A dumbbell-type CPW transmission-line structure has been proposed to improve the return loss of the transmission line between a driver IC and flip-chip-bonding VCSEL(Vertical Cavity Surface Emitting Laser) in a hybrid opto-electric circuit board(OECB). The proposed structure used a pair of dummy ground solder balls on the ground lines for flip-chip bonding of the VCSEL and designed the dumbbell-type CPW transmission line to improve reflection characteristics. The simulated results revealed that the return loss of the dumbbell-type CPW transmission line was 13-dB lower than the conventional CPW transmission line. A 4-dB improvement in the return loss was obtained using the dummy ground solder balls on the ground lines. The variation rate of the reflection characteristic with the variation of terminal impedances of the transmission line (at the output terminal of the driver IC and the input terminal of the VCSEL) is about ${\pm}2.5\;dB$.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.220-224
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• 2000

AlGaAs/GaAs HBT를 이용하여 1.9 GHz 대역 2단 MMIC 전력증폭기를 설계하였다. HBT의 실측 S 파라미터를 이용하여 정합회로를 설계하였으며, 목적에 따라 적절한 형태의 출력 정합 회로를 하이브리드 형태로 칩 외부에 부가할 수 있도록 설계하였다. HBT의 실측정 S 파라미터의 fitting을 통하여 비선형 등가모델을 추출하였고, load-pull 시뮬레이션으로 최대 출력 정합 임피던스를 결정하였다. 시뮬레이션 결과, 29 dBm의 출력 전력, 40 %의 전력 부가 효율, 그리고 16 dB의 전력 이득을 얻었다.

• Electronics and Telecommunications Trends
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• v.6 no.3
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• pp.3-12
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• 1991

현재 전자장비는 대부분 반도체소자로 구성되어 있어 이들 소자의 신뢰성이 매우 중요하다. 반도체소자의 신뢰성은 고장률로 표현되는데 실질적인 고장률은 사용현장에서 수집된 데이터에서 산출되지만 데이터 수집기간이 길고, 고장원인이 불분명하며, 수적으로도 빈약한 실정이다. 따라서 본고에서는 MIL-HDBK-217E의 고장률예측 모델을 이용하여 반도체소자를 제조기술, 패키지형태, 칩접착 상태별로 구분하여 고장률을 산출하였다.