• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.05a
• /
• pp.486-489
• /
• 2010

This paper describes a layered LDPC decoder which supports block length of 1,944 bits and code rate 1/2 for IEEE 802.11n WLAN standard. To reduce the hardware complexity, the min-sum algorithm and layered architecture is adopted. A novel memory reduction technique suitable for min-sum algorithm reduces memory size by 75% compared with conventional method. The designed processor has 200,400 gates and 19,400 bits memory, and it is verified by FPGA implementation. The estimated throughput is about 200 Mbps at 120 MHz clock by using Xilinx Virtex-4 FPGA device.

• Proceedings of the Korean Operations and Management Science Society Conference
• /
• 1998.10a
• /
• pp.275-277
• /
• 1998

최근 Ravi와 Goemanns는 즉 전체 길이의 합이 일정한 값을 넘지 않는 최소비용신장나무(minimum spanning tree problem)를 구하는 문제의 (1+$\varepsilon$,1)-근사해를 구할 수 있는 알고리듬을 제시하였다. 즉 비용은 최적을 보장하지만 전체길이 제약조건은 근사적으로 만족하는 해를 생성한다. 그러나 이러한 알고리듬은 문제의 비가능해를 생성 할 수 있으며 1/$\varepsilon$에 대하여 지수함수의 수행시간을 갖는다. 본 논문에서는 Ravi와 Geomanns의 알고리듬을 실용적으로 변형하여 전체 길이 제약조건을 정확히 만족하며, 그 비용은 최적비용과의 차이가 호의 비용 중 최대값을 넘지 않도록 보장하는 강성다항식 알고리듬을 제사한다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.6
• /
• pp.1355-1362
• /
• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.5
• /
• pp.31-40
• /
• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2009.11a
• /
• pp.11-14
• /
• 2009

기존의 반이중방식 단방향 중계 네트워크는 하나의 정보를 두 개의 시간 슬롯 동안에 보내므로 주파수 효율에서 감소가 생기게 된다. 이러한 주파수 효율의 감소를 막기 위해 제안된 양방향 중계 네트워크는 중계기에 중첩 부호화 또는 네트워크 부호화를 적용함으로써 단방향 중계 네트워크에 비해 향상된 주파수 효율을 제공한다. 한편, OFDMA 네트워크는 사용자에게 부반송파, 전력 등의 자원을 적응적으로 할당하여 네트워크의 성능 향상을 얻을 수 있다. 본 논문에서는 다중사용자 다중중계기 양방향 OFDMA 중계 네트워크를 위한 새로운 적응적 부반송파 할당 알고리듬을 제안한다. 먼저 모든 사용자 쌍에 대한 달성 합 전송속도(achievable sum-rate over all user pairs)를 최대화하기 위한 최적화 문제를 정형화한다. 시스템의 수명을 늘이고 각 사용자의 최소 전송속도를 보장하기 위해 공정성 제한을 고려한다. 그리고 이로부터 새로운 적응적 부반송파 할당 알고리듬을 제안한다. 모의실험을 통해 제안된 알고리듬이 정적 알고리듬과 그리디 알고리듬, 두 알고리듬 모두 보다 훨씬 낮은 불능확률을 얻음을 확인한다.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.12 no.2
• /
• pp.12-21
• /
• 2013

This study developed searching network reduction algorithm for reduce shortest path searching time. Developed algorithm is searching nodes that have the including possibility of less weights path than temporal path that consists minimum number of nodes and minimum sum of the straight line distances. The node that has the including possibility of shortest path is the node that the sum of straight line distance from start node and straight line distance to target node is less than the value that temporary path's weights divided by minimum weights units. If searching network reconstitutes only these nodes, the time of shortest path searching will be reduced. This developed algorithm has much effectiveness that start node and target node is close in large network.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.4
• /
• pp.876-884
• /
• 2014

A hardware design of LDPC decoder which is based on the improved normalized min-sum(INMS) decoding algorithm is described in this paper. The designed LDPC decoder supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. The decoding function unit(DFU) which is a main arithmetic block is implemented using sign-magnitude(SM) arithmetic and INMS decoding algorithm to optimize hardware complexity and decoding performance. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 100 MHz clock has 284,409 gates and RAM of 62,976 bits, and it is verified by FPGA implementation. The estimated performance depending on code rate and block length is about 82~218 Mbps at 100 MHz@1.8V.

• Korean Journal of Remote Sensing
• /
• v.18 no.2
• /
• pp.107-116
• /
• 2002

A hybrid image segmentation algorithm is proposed which integrates edge-based and region-based techniques through the watershed algorithm. First, by using mean curvature diffusion coupled to min/max flow, noise is eliminated and thin edges are preserved. After images are segmented by watershed algorithm, the segmented regions are combined with neighbor regions. Region adjacency graph (RAG) is employed to analyze the relationship among the segmented regions. The graph nodes and edge costs in RAG correspond to segmented regions and dissimilarities between two adjacent regions respectively. After the most similar pair of regions is determined by searching minimum cost RAG edge, regions are merged and the RAG is updated. The proposed method efficiently reduces noise and provides one-pixel wide, closed contours.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.4A
• /
• pp.414-422
• /
• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.10a
• /
• pp.405-409
• /
• 2009

In this paper, the effects of LLR (Log-Likelihood Ratio) approximation on LDPC (Low-Density Parity-Check) decoder performance are analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by MATLAB, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate (BER) performance of LDCP decoder. The parity check matrix for IEEE 802.11n standard which has block length of 1,944 bits and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (7,5).