• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.70-78
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• 2009

This paper addresses the analysis and the design optimization of differential interconnects for high-speed Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, and time-domain transient simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.879-886
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• 2008

This paper addresses the analysis and the design optimization of differential interconnects for Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential flexible printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, time-domain transient simulations, and S-parameter simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. The 10% change in trace width produced change of approximately 6% and 5.6% in differential impedance for trace thickness of $17.5{\mu}m$ and $35{\mu}m$, respectively. The change in the trace space showed a little change. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.761-764
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• 2007

This paper addresses the analysis and the design optimization of differential interconnects for Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and πace space in differential flexible printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, time-domain transient simulations, and S-parameter simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.6
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• pp.81-86
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• 2006

Routing signal lines in PCB, line shapes would be straight or bent. time-domain and frequency-domain evaluation of the signal property and interference are archived by precise Modeling of differential signal line. Some of CAD tools can extract equivalent circuit model parameters. but it takes a long time and heavy loads. This paper introduces a basic RLC equivalent circuit model parameter extraction technique for bent differential structures using genetic algorithm by this technique, we can model equivalent circuit of bent differential structures more faster.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.1-6
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• 2005

A dual-level low voltage differential signalling (DLVDS) circuit is proposed aiming at reducing transmission lines for LCD driver IC. In the proposed circuit, we apply a couple of primitive data to DLVDS circuit as inputs. The transmitter converts two inputs to two kinds of fully differential level signals. In this circuit, two transmission lines are sufficient to transfer two primitive inputs while keeping the LVDS feature. The receiver recovers The original input data through a level decoding circuit. We fabricated the proposed circuit using $0.25\mu m$ CMOS technology. The resultant circuit shows 1-Gbps/2-line data rate and 35-mW power consumption at 2.5V supply voltage, respectively.

• The Journal of the Korea Contents Association
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• v.6 no.3
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• pp.38-45
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• 2006

A dual-level low voltage differential signalling (DLVDS) circuit is proposed aiming at reducing transmission lines for a LCD driver IC. We apply two data to the proposed DLVDS circuit as inputs. Then, the transmitter converts two inputs to two kinds of fully differential signals. In this circuit, two transmission lines are sufficient to transfer two inputs while keeping the LVDS feature. However, the circuit has a common mode bias fluctuation due to difference of the input bias and the reference bias. We compensate the common mode bias fluctuation using a feedback circuit of the current source bias. The receiver recovers the original input data through a level decoding circuit. We fabricated the proposed circuit using $0.25{\mu}m$ CMOS technology. The simulation results of proposed circuit shows 1-Gbps/2-line data rate and 35mW power consumption at 2.5V supply voltage, respectively.

• Journal of Advanced Navigation Technology
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• v.17 no.2
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• pp.196-201
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• 2013

In this paper, a dual-mode balanced filter with symmetric coupled composite right/left-handed transmission line is introduced. Unlike the other symmetric structure, this configuration has the ability to operate under both common- and differential-mode excitation. These properties are achievable through providing physical short circuit by means of ground vias at the center of each unit-cell along the symmetry plane of the structure. Because the CRLH unit-cells are operated under both common- and differential-mode excitation, we implemented a balanced filter using these properties. To validity these features, a five-cell four port coupled CRLH-TL is simulated, fabricated and measured and the obtained performances agree with the simulation results under both common- and differential-mode excitation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.59-67
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• 2007

This paper presents a low power dual-level low voltage differential signaling (DLVDS) technique using current source switching for LCD driver ICs in portable products. The transmitter makes dual level signal that has two different level signal 400mVpp and 250mVpp while keeping the advantages of LVDS. The decoding circuit recovers the primary signal from DLVDS. The low power DLVDS is implemented using a $0.25{\mu}m$ CMOS process under 2.5V supply. The proposed circuit shows 800Mbps/2-line data rate and 9mW, 11.5mW power consumptions in transmitter and receiver, respectively. The proposed DLVDS scheme reduce power consumption dramatically compare with conventional one.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.213-219
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• 2012

In this paper, we suggested the method of signal integrity for noises and distortion signal generated between high speed information transmission modules by external effects. Suggested method for signal integrity of impedance matching to remove transmission line distortion, We divided the impedance matching between the transmitter and the receiver module with the single line and differential line methods after confirmed the improvement of signal distortions through ADS simulation. the experimental results indicated that it is possible to keep signal integrity without signal distortions by matching the optimal termination impedance which are considering the signal delay of transmission line for using the high-performance modules.

• Proceedings of the Korea Information Processing Society Conference
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• 2018.05a
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• pp.19-21
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• 2018

컴퓨팅 시스템의 고속화와 더불어 시스템, 서버의 내외부에서 다양한 미디엄에 기반 한 고속 신호 연결의 필요성이 증대되고 있다. Gbps 급 이상의 전송속도를 요하는 시스템 네트워크, 서버 시스템 버스 등의 활용에 있어서, 구리선 기반의 고속 케이블 미디엄이 널리 사용되고 있으며, 이들 케이블 미디엄의 속도는 점차 향상하고 있는 추세이다. 본 논문에서는, Gbps급의 고속 시스템 버스에 대한 케이블 미디엄 기반의 신호 송수신 실험을 통하여, 고속 신호전송에 사용 가능한 케이블 미디엄의 신호 특성 및 성능을 비교 분석 한다. Gbps급 전송의 실험을 위하여 차동 신호 당 10 Gbps급 이상의 전송속도를 가지는 microQSFP, Mini SAS HD, Passive Copper 케이블 미디엄을 사용하는 HW를 제작하여 실험하였다. 제작된 HD를 기반으로 8Gbps급 고속 신호의 병렬 전송 실험을 통하여 케이블 미디엄의 성능을 평가 하였다. 평가 결과, Passive Copper 케이블을 포함하여 모든 케이블 미디엄이 8Gbps 이상의 고속 전송에 적합함을 확인하였다.