• Title/Summary/Keyword: 차단 회로

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A study on the Functional Properties of Polyester Fiber Treated Titanium Dioxide Photocatalyst (이산화티타늄 광촉매를 처리한 Polyester 섬유의 기능성 연구)

  • Choi, Sei Young
    • Elastomers and Composites
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    • v.49 no.4
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    • pp.336-340
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    • 2014
  • The functionality such as deodorant, antibacterial, ultraviolet shielding of titanium dioxide self-actuated photocatalyst $Weltouch^{TM}$ treated polyester fiber was characterized in conditions without light. The deodorizing capacity was maintained more than 97% reduction irrespective of before washing and after 20 times repeated washing, and antimicrobial capacity was also retained more than 99.9% reduction. Titanium dioxide self-actuated photocatalyst was still maintained to the surface of polyester fiber without separation even after 20 times repeated washing. According to washing durability of polyester fiber, the reduction effect for ammonia was still retained even after 20 times repeated washing as much as before washing. The ultraviolet shielding capacity was still maintained at least 83% irrespective of before washing and 20 times repeated washing.

The Latchup Shutdown Circuit of LVTSCR to Protect the ESD (ESD 보호를 위한 LVTSCR의 래치업 차폐회로)

  • Jung, Min-Chul;Yoon, Jee-Young;Ryu, Jang-Woo;Sung, Man-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.07a
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    • pp.178-179
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    • 2005
  • ESD(Electrostatic Discharge) 보호에 응용되는 소자는 ESD가 발생했을 때, 빠르게 턴-온되어 외부로부터 EOS(Electric OverStress)를 차단함으로서 집적회로 내부의 코어를 보호해 주어야 한다. 이러한 기능에 충실한 LVTSCR(Low-Voltage Silicon Controlled Rectifier)은 트리거링 전압을 기존의 SCR보다 낮추어 ESD에 대해 민감한 반응을 할 수 있도록 개선한 소자이다. 그러나 트리거링 전압을 낮추면서 래치업 전압 또한 낮아지는 특성이 trade-off 관계로 맞물려 있어, LVTSCR의 단점인 낮은 래치업 전압을 효과적으로 다루는 것이 큰 이슈가 되고 있다. 본 논문에서는 LVTSCR의 ESD 보호에 대한 응용시 발생 가능한 래치업을 차폐하는 회로적 방법을 제시하였다. 제시된 새로운 구조의 차폐회로는 LVTSCR에서 래치업이 발생했을 때, 천이 전류를 감지하여 래치업이 발생되는 소자에 대한 전원을 스스로 차폐시켜 래치업에 대한 안정성을 시뮬레이션으로 검증하였다.

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A Design of the UWB Bandpass Filter with a Good Performance of the Stopband, and Notched Band in Passband (우수한 차단 대역 특성과 통과 대역 내에 저지 대역을 갖는 UWB 대역 통과 필터 설계)

  • An, Jae-Min;Kim, Yu-Seon;Pyo, Hyun-Seong;Lee, Hye-Sun;Lim, Yeong-Seog
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.1
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    • pp.28-35
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    • 2010
  • In this paper, we designed and fabricated a ultra-wideband(UWB) bandpass filter with a good performance of a stopband, and a notched band in passband. The transformed equivalent circuit of the highpass filter was realized by distributed element. A wide-passband with 3-dB fractional bandwidth of more than 100 % was achieved by using optimum response of the HPF. For improving lower and upper stopband characteristic, a cross coupling between feed lines was employed, which was analyzed by desegmentation technique. In order to reject interference of Wireless LAN and Hyper LAN(5.15~5.825 GHz), the narrow notched(rejection) band was realized by a spurline. The fabricated BPF indicated the passband from 3.1 to 10.55 GHz and the flat group delay of less than 0.94 ns over the entire passband except the rejection band. The filter shown sharp attenuation both inside and outside the band and notched band from 5.2 to 6.12 GHz.

A Technique for Reducing the Size of Microwave Amplifiers using Spiral-Shaped Defected Ground Structure (맴돌이형 결함접지구조를 이용한 마이크로파 증폭기의 소형화 방법)

  • Lim, Jong-Sik;Jeong, Yong-Chae;Ahn, Dal;Nam, Sang-Wook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.9
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    • pp.904-911
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    • 2003
  • A new method to reduce the size of microwave amplifiers spiral-shaped defected ground structure(Spiral-DGS) is proposed. A microstrip line having Spiral-DGS on the ground plane produces increased slow-wave factor and electrical length for the fixed physical length. In addition, it provides an excellent rejection characteristic for a finite frequency band like band rejection filters. The rejection band is used for rejecting harmonic components of amplifiers. The reduced microstrip line lengths in matching networks by Spiral-DGS are 39 % and 44 % of the original ones in input and output matching networks, respectively. It is shown that the measured S-parameters of the reduced amplifier agree well with those of the original amplifier. The measured second harmonic of the reduced amplifier is much less than that of the original amplifier by at least 10 dB. The same technique is applied to reject the third harmonic using the proper Spiral-DGS for the third harmonic frequency. The measured third harmonic is smaller than that of the original amplifier by 25 dB.

The Heart Rate and ECG Changes after Endoscopic Thoracic Sympathectomy in Patients with Primary Hyperhidrosis (원발성 다한증 환자에서 흉부 교감 신경 차단술 후의 심박동수 및 심전도 변화)

  • Kim, Jae-Jun;Kim, Young-Du;Park, Chan-Beom;Moon, Seok-Whan;Cho, Deog-Gon;Sa, Young-Jo;Seo, Jong-Hee;Kim, Chi-Kyeong
    • Journal of Chest Surgery
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    • v.42 no.2
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    • pp.214-219
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    • 2009
  • Background: Primary focal hyperhidrosis is characterized by overactivity of the sympathetic nervous function, and this has been effectively treated with endoscopic thoracic sympathetic denervation (ESD). The imbalance of sympathetic and parasympathetic nervous system that's created by ESD may affect the heart, lung and other thoracic organs. We analyzed the heart rate and ECG changes after performing ESD at our hospital, and this is the first such study that has been conducted on this. Material and Method: Of the 263 patients who underwent ESD between October 1996 and October 2006, 130 had ECG before and after ESD, and they were classified into 3 groups according to the level of ESD: Group I (n=40) patients underwent ESD at the 2nd rib (T2ESD), Group II (n=80) at the 3rd rib (T3ESD) and Group III (n=10) at the 4th rib (T4ESD). Result: There was no mortality or major morbidity. Heart rate (HR) was significantly decreased from $71.6{\pm}10.6/min\;to\;66.8{\pm}10.2/min$ after ESD (p<0.01); however, the PR (from $148.6{\pm}21.2$ msec to $152.8{\pm}20.5$ msec) and QTc (from $399.2{\pm}15.4$ msec to $404.0{\pm}15.1$ msec) intervals were significantly increased after ESD in the patients who suffered with primary hyperhidrosis (p<0.01). According to the level of ESD, there were significant changes in the HR and QTc interval in group I (T2ESD), the HR and PR interval in group II and the QTc interval in Group III. Conclusion: There were significant changes in the heart rate and ECG findings after ESD. The thoracic sympathetic denervation of T2, T3 and T4 affected the electrical activity of the heart at the resting state.

A Development of Intelligent Controller for Phase Control in Main Circuit Breaker (주회로차단기 투입전원 위상제어를 위한 지능형 제어기 개발)

  • Oh, Yong-Kuk;Kim, Jae-Won;Ryu, Joon-Hyoung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.18 no.11
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    • pp.755-761
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    • 2017
  • In railways powered by AC power, the main circuit breaker (MCB) is used for supplying the electric power to the catenary of the vehicle. Generally, the main circuit breaker is located between the pantograph and the main transformer, and the phase of the power applied to the vehicle changes according to the operation timing of the main circuit breaker. The operation of the main circuit breaker should be actively controlled according to the phase of the power source, since the phase of the power causes unintended transient states in the vehicle's electrical system in the form of an inrush current and surge voltage. However, the MCB has a delay time when it operates which is not constant. Therefore, an intelligent controller is needed to predict the operation delay time and control the opening and closing of the MCB.

Dual Mode Boost Converter for Energy Harvesting (에너지 하베스팅을 위한 이중 모드 부스트 컨버터)

  • Park, Hyung-Ryul;Yeo, Jae-Jin;Roh, JeongJin
    • Journal of IKEEE
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    • v.19 no.4
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    • pp.573-582
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    • 2015
  • This paper presents the design of dual mode boost converter for energy harvesting. The designed converter boosts low voltage from energy harvester through a startup circuit. When the voltage goes above predefined value, supplied voltage to startup circuit is blocked by voltage detector. Boost controller makes the boosted voltage into $V_{OUT}$. The proposed circuit consists of oscillator for charge pump, charge pump, pulse generator, voltage detector, and boost controller. The proposed converter is designed and fabricated using a $0.18{\mu}m$ CMOS process. The designed circuit shows that minimum input voltage is 600mV, output is 3V and startup time is 20ms. The boost converter achieves 47% efficiency at a load current of 3mA.

A Study on the Stabilization of Generating Negative Voltage for IT Equipments using Microcontroller (마이크로컨트롤러를 이용한 IT 기기용 마이너스 전압 생성의 안정화에 관한 연구)

  • Lee, Hyun-Chang
    • Journal of Convergence for Information Technology
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    • v.11 no.6
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    • pp.7-13
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    • 2021
  • In this paper, the function of starting the negative voltage used in the IT equipment when it is generated and the method of controlling it using a microcontroller for the function to detect the overload and respond to it are presented. To do this, the limitations of the existing negative voltage generation circuit and the problems that occur during overload were analyzed, and a circuit that detects and controls the overload condition without a separate current sensing circuit was presented. In order to confirm the effect of the proposed method, an experiment was conducted by configuring an experimental circuit. As a result of the experiment, compared to the existing negative voltage generation circuit, which falls into a latch-up state when overloaded and enters a dangerous state, the proposed circuit detects this, stop the operation of the circuit, and informs the user of such an abnormal state to take action. have. In addition, since the starting point of the circuit is determined according to the system state, the experimental result was confirmed that the starting time was significantly shortened by about 23% compared to the time switch method.

Digital Phase-Locked Loop(DPLL) Technique for UPS (무정전 전원장치용 디지털 위상동기화 기법)

  • 김제홍;최재호
    • The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.11 no.3
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    • pp.106-113
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    • 1997
  • In uninterruptible power supply(UPS), a high speed phase control is usually required to compensate transients in the output voltage at the instant of transfer from the ac line to the inverter when the ac line fails or backs to the ac line in case of the inverter fails. To overcome this problem, this paper pre¬sents the closed digital phase-locked loop(DPLL) techniques designed by full software with TMS320C31 digital signal processor and describes the functional operation of the proposed DPLL. Fi¬nally, the performance of the proposed DPLL is shown and discussed through simulation and experiment.

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155.52 Mbps High Performance CMOS Receiver for STM-1 Application (STM-1급 155.52 Mbps 고성능 CMOS 리시버의 구현)

  • 채상훈;정희범
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.6B
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    • pp.1074-1079
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    • 1999
  • A high performance CMOS receiver for 155.52 Mbps STM-1 digital communication has been designed and fabricated. The ASIC operates properly with 155.52 MHz clock frequency in case of the data loss due to some system error such as transmission line open or data transfer fail. Also it operates properly in case the system starts after the power failure or system maintenance. The designed circuit has especially PLL based self oscillation loop which operates on abnormal environment which is added to main oscillation loop. The measured results show that the circuit operates well with 153.52 MHz clock frequency not only on normal environment but also on abnormal environment. Rms jitter of the PLL loop is about 23 ps.

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