• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.21-26
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• 2008

In this paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuits are implemented with 0.35um CMOS process technology. Locking dynamics is accomplished with instantaneous feature and data are sampled at an optimal timing. This is realized by seven different delay configurations, which are generated from precisely-controlled delay buffers. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.60.1-60.1
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• 2011

비정질 indium-gallium-zinc-oxide (a-IGZO)는 thin film transistor (TFT)에 적용되는 대표적인 active layer로써 높은 이동도를 갖고, 도핑 농도의 제어가 용이하며 낮은 온도에서도 대면적에 증착할 수 있는 특성을 가지고 있다. 특히 저온에서 대면적 증착이 가능한 장점을 갖고 있어 LCD 분야뿐만 아니라 다양한 분야에서 상용화하려는 연구가 시도되고 있다. a-IGZO를 구성하는 물질 중에 이동도에 중요한 역할을 미치는 In은 대표적인 투명전극물질인 indium-tin oxide (ITO)에서 고전류 구동에 의한 확산이 널리 알려져 이에 대한 증명과 개선을 위한 연구가 진행되고 있다. 보고된 결과에 따르면 device에 지속적인 구동 전압을 가했을 때 In이 유기층로 확산되어 organic light emitting diode(OLED)의 성능을 저하시키는 것으로 알려져 있다. 따라서, a-IGZO에서도 고전류 구동에 의한 indium의 이동이 필수불가결하다고 판단된다. 본 연구에서는 a-IGZO TFT에 고전압 구동을 반복적으로 시행함으로써 발생하는 전기적 특성의 변화를 확인하였고, 동일한 소자의 전극과 채널 사이의 계면에서 In 분포를 energy dispersive spectrometer (EDS)로 관찰하여 In 분포와 전기적 특성 간의 상관관계에 대해 연구하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.38-45
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• 2000

In this paper, an approach of modeling the optical interconnection system by SPICE simulation is presented. SPICE simulations with equivalent circuit models for optical devices are performed in a stable manner. From the simulated results, eye diagrams for receiver output and BER are obtained. Timing jitter due to laser diode turn-on delay effects can be found under various bias conditions. Using this approach, various system parameters such as bit rate, BER, dissipated transmitter power, and bias conditions can be optimized. It is expected that this approach will find useful applications such as Gigabit Ethernet and ATM.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.384-389
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• 2003

A new two-step soft-output Viterbi algorithm (SOVA) decoder architecture is presented. A significant reduction in the decoding latency can be achieved through the use of the dual-port RAM in the survivor memory structure of the trace-back unit. The system complexity can be lowered due to the determination of the absolute value of the path metric differences inside the add-compare-select (ACS) unit. The proposed SOVA architecture was verified successfully by the functional simulation of Verilog HDL modeling and the FPGA prototyping. The SOVA decoder achieves a data rate very close to that of the conventional Viterbi Algorithm (VA) decoder and the resource consumption of the realized SOVA decoder is only one and a half times larger than that of the conventional VA decoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6A
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• pp.913-919
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• 1999

A systematic synthesis process is presented for the design of ADSL POTS splitters. It consists of a low-pass filter formed by a single-ended inductor, balanced inductor, and balance tightly coupled transformer. This three low-pass filters has been simulation. Simulation results show agreement of frequency characteristics. Therefore, POTS splitters using a commercial balance tightly coupled transformer are designed for the applications of ADSL system. The experimental results show that POTS splitter in the ADSL system has ripple decibel of less than $\pm$0.5 dB over a frequency range from 0.2 kHz to 3.4 kHz(or an audio band frequency) and delay distortion of less than 130 $mutextrm{s}$ over a frequency range from 0.6 kHz to 3.2 kHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.7
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• pp.612-619
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• 2016

In this paper, a dual band electrical beam tilting array antenna with bi-directional directivity is designed. Radiating element operates at dual-resonance frequencies and is designed as planar dipole using PCB. In order to tilt the main beam, the phase delay line is designed by use of only the phase shifting line of a $50\Omega$ microstrip line for broadband. The designed antenna has tilting angle of $0^{\circ}$ to ${\pm}8^{\circ}$. For validation of the designed antenna specification, the array antenna is fabricated and the performances are measured. Comparison between theory and experiment shows good agreement.

• Laser Solutions
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• v.17 no.4
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• pp.20-23
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• 2014

In printed electronics, printing rolls are used to transfer electronic ink onto a flexible substrate. Generally printing rolls are patterned in microscale by the indirect laser method. Since based on the wet etch process, the indirect method is neither environment-friendly nor suitable for making a printing roll with patterns narrower than $20{\mu}m$. In this paper, we have directly engraved micro-patterns into a Zn-coated metal specimens using a picosecond laser in order both to engrave $10{\mu}m$-wide patterns and to improve the pattern profile. Experiments showed that it is possible to engrave $10{\mu}m$-wide patterns with an a rectangular-shaped profile which is necessary for the dimensionally accurate printing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.76-82
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• 2002

This paper presents a quaternary-binary decoder, a quaternary logic current buffer, and a quaternary logic full-adder using current-mode multiple-valued logic CMOS circuits. Proposed full-adder requires only 15 MOSFET, 60.5% and 48.3% decrease of devices are achieved compared with conventional binary CMOS full-adder and Current's full-adder. Therefore, decrease of area and internal nods are achieved. Designed circuits are simulated and verified by HSPICE. Proposed full-adder has 1.5 ns of propagation delay and 0.42㎽ of power consumption. Also, proposed full-adder can easily adapted to binary system by use of encoder, designed decoder and designed current buffer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.6
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• pp.539-547
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• 1992

Considering the field of high frequency or broad-band signal filtering with high speed, we pro-pose optical fiber filters which consist of directional couplers and optical fiber delay elements. Fiber delay line signal processor Is operated with Incoherent optical carrier because of Its simplicity. Due to the characteristics of the directional coupler which Is basic element of optical fiber filter a new design method which Is different from that of usual digital filter is required. By considering the characteristics of directional coupler and in order to make good use of the optical signal energy, we have given the design formulae and the conditions of optical fiber filters for the direct and the lattice form.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.660-667
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• 2000

This paper aims at analyzing the traffic of CDMA base station. RTD(Round Trip Delay) method, used for the study, is one of the developed tool for calculating the call setup time between the BTS(Base Station TransceiverSubsystem) and mobile station.We compare the calculated call setup time in air with the field experiments.And we suggest the RTD method for dividing the traffic of the connected repeater from that of the BTS, andwe can testify it by the experiment which analyze the difference of the received time between the base stationand the repeater including the forced delay elements.