• Title/Summary/Keyword: 증폭기

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A study on the error probability of optical system using kappa square analysis method (카파자승해석법을 이용한 광시스템의 에러 확률에 관한 연구)

  • Ha, Eun-Sil
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.9
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    • pp.6254-6259
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    • 2015
  • On the optical system and the system itself of the noise of the noise from the outside always present. This noise is to function as reducing performance of the optical system. Therefore, the probability of error, thereby changing the system. In this paper, the error probability of the optical system due to changes in various values by introducing the characteristic variable the value of the optical system was calculated using the ${\kappa}$-square method. Was confirmed also in accordance with the calculation result is an error probability of the optical system changes, it was confirmed that when the value of the holding case for holding the standard about 400 Lux on the probability of the optical system. This case was found to be an optical system using a light source with a low output, so that means the smaller output is no problem to maintain the error probability value of the optical system is large. This means that more effective and less expensive to implement because it means that the optical system does not require the use of pre-amplifier for amplifying the signal at the receiving end of an optical system using a light source with a low output when the normal case.

Measurement and Analysis of Magnetic Fields and Induced Voltages Caused by Home Appliances (가정용 전기기구에서 발생하는 자장과 유도전압의 측정과 분석)

  • 이복희;이동문;장영태;장근철;엄주홍;강성만;이승칠;박정용
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.16 no.6
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    • pp.51-59
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    • 2002
  • This paper deals with the measurement and analysis of the induced voltages and magnetic fields caused by the operation of home appliances. The induced voltage and magnetic field measurement circuit used in this work consists of the induction coil, the operational preamplifier and the active integrator. Television set and monitors for personal computer cause strong magnetic fields rich in harmonics and high induced voltages by using the switching power suppliers. The strong magnetic field intensity and high induced voltage were created by 14" television set, and their values are 2.1 [$\mu$Tp-p]and 140 [mVp-p]at the distance of 0.4 [m], respectively. However, the induced voltage per unit magnetic field intensity was created by 17" monitor for personal computer and the measured data was approximately 560[mV/$\mu$T]at the same distance. distance.

Design of a Phase Splitter(2.4[GHz]) using Differential Amplifier (자동증폭기를 이용한 위상분상기(Phase Splitter) 설계)

  • Roh, Hee-Jung;Seo, Choon-Weon
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.22 no.6
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    • pp.14-17
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    • 2008
  • This paper describes the simulation of a phase splitter for the design of Chireix Outphasing power amplifier. Phase splitter separate the input signal with $0[^{\circ}]$ into the signal with $+90[^{\circ}]$ and $-90[^{\circ}]$ Chireix Outphasing power amplifier get a linearized output from the signal amplifying and combining the separated signal with the phase of $+90[^{\circ}]$ and $-90[^{\circ}]$ of the phase splitter. phase splitter is the core device when designing Chireix Outphasing power amplifier. It is very difficult to design phase splitter with the difference of $90[^{\circ}]$. This phase splitter is used to design the difference of $180[^{\circ}]((90[^{\circ}]+{\alpha}),\;-(90[^{\circ}])+{\alpha}))$ using simulation tool and a differential amplifier.

New On-Chip RF BIST(Built-In Self Test) Scheme and Circuit Design for Defect Detection of RF Front End (RF Front End의 결함 검출을 위한 새로운 온 칩 RF BIST 구조 및 회로 설계)

  • 류지열;노석호
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.2
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    • pp.449-455
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    • 2004
  • This paper presents a novel defect detection method for one chip RF front end with fault detection circuits using input matching measurement. We present a BIST circuit using 40.25{\mu}m$ CMOS technology. We monitor the input transient voltage of the RF front end to differentiate faulty and fault-free RF front end. Catastrophic as well as parametric variation fault models are used to simulate the faulty response of the RF front end. This technique has several advantages with respect to the standard approach based on current test stimulus and frequency domain measurement. Because DUT and fault detection circuits are implemented in the same chip, this test technique only requires use of digital voltmeter (RMS meter) and RF voltage source generator for simpleand inexpensive testing.

Design of Antenna for Beam Scanning for Dual-Band base station (이중대역 기지국용 빔 스캔 안테나 설계)

  • Ko Jin-Hyun;Jang Jae-Su;Ha Jae-Kwon;Park Sae-Houn
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2006.05a
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    • pp.632-636
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    • 2006
  • It is needed to use the beam scanning to control the cell coverage of the base station considering operation conditions, season, time period, radiation character and mobility of customers and vehicles for varied wireless communication service and quality improvement. This paper proposes a mobile antenna system which can obtain the characteristics of the beam scanning by controlling the directivity depending on the operation condition. Radiation block is made of 2 sub-array of $1\times3$ patched antennas for ITS of 5.8GHZ bandwidth with the gain of 13dBi, and of 2 sub-array of single patched antenna for WiBro of 2.3GHZ bandwidth with the gain of 12dBi. RF module is made of a switch, an amplifier, a PAD, a 3-Bit phase shifter, and a power divider. The system is able to control the beam tilting with electronic methode by using 3-bit phase shifter$(45^{\circ},\;90^{\circ},\;180^{\circ})$.

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Measurement of Blood Flow Variation using Impedance Method (임피던스법을 이용한 혈류량 변화 측정)

  • Jeong Do-Un;Kang Seong-Chul;Jeon Gye-Rock
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2006.05a
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    • pp.693-696
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    • 2006
  • In this study, we made the system to measure variation of blood flow using bio-electrical impedance analysis method. The system, which could measure variation of impedance according to pressure change by artificial pressure, consists of pressure measurement and impedance measurement by 4-electrode method. Pressure measurement splits into semiconducting pressure sensor and electronic circuit for processing output signal. In addition, impedance measurement splits into constant current source circuit and lock-in amplifier for detection impedance signal. We experimented feature of impedance measurement using standard resistance to evaluate the system characteristic. As well as, we experimented to estimate variation of blood flow by measuring impedance and blood flow resistance ratio using mean arterial pressure and variation of blood flow with experimental group. As result of this study, blood flow resistance ratio and variation of blood flow were definitely in inverse proportion and were -0.96776 as correlation coefficient by correlation analysis.

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MASK ROM IP Design Using Printed CMOS Process Technology (Printed CMOS 공정기술을 이용한 MASK ROM 설계)

  • Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.05a
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    • pp.788-791
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    • 2010
  • We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.

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Design of an Asynchronous eFuse One-Time Programmable Memory IP of 1 Kilo Bits Based on a Logic Process (Logic 공정 기반의 비동기식 1Kb eFuse OTP 메모리 IP 설계)

  • Lee, Jae-Hyung;Kang, Min-Cheol;Jin, Liyan;Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.7
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    • pp.1371-1378
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    • 2009
  • We propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at program and read mode, and reduces an operation current at read mode by reducing parasitic capacitances existing at both WL and BL. Asynchronous interface, separate I/O, BL SA circuit of digital sensing method are used for a low-power and small-area eFuse OTP memory IP. It is shown by a computer simulation that operation currents at a logic power supply voltage of VDD and at I/O interface power supply voltage of VIO are 349.5${\mu}$A and 3.3${\mu}$A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18${\mu}$m generic process is 300 ${\times}$557${\mu}m^2$.

Power optimization of optical 40 wavelength division multiplexing channels at 3000 km transmission for link span variation (40 채널 파장 다중화 광신호 3000 km 전송에서 링크 구간 거리에 따른 광신호 세기 최적화)

  • Choi, Bo-Hun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.1
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    • pp.197-203
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    • 2013
  • Optical power optimization of 10 Gbps 40 wavelength division multiplexing channels was analyzed at the 3000 km long-haul transmission distance when the link span distance was changed between 40 km and 140 km. The signal performance of the transmission was obtained as a Q value and it was compared when input power into SSMF and input power into DCF on the transmission link were changed. The optimized input power into SSMF increased linearly to link span distance with 1 dB/km. The optimized power into DCF increased linearly with 0.5 dB/km up to 100 km link span, but it had no variation at longer link span than 100 km.

PSPICE analysis of the Lorenz circuit using the MOS resistor (MOS 가변저항을 이용한 로렌츠 회로의 PSPICE 해석)

  • Ji, Sung-Hyun;Kim, Boo-Kang;Nam, Sang-Guk;Nguyen, Van Ha;Park, Yong Su;Song, Han Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.2
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    • pp.1348-1354
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    • 2015
  • In this paper, chaotic circuit of the voltage controlled Lorentz system for engineering applications has been designed and implemented in an electronic circuit. The proposed circuit consists of MOS variable resistor, multipliers, capacitors, fixed resistors and operational amplifiers. The circuit was analysed by PSPICE program. PSPICE simulation results show that chaotic dynamics of the circuit can be controlled by the MOS variable resistor through time series analysis, frequency analysis and phase diagrams. Also, we implemented the proposed circuit in an electronic hardware system with discrete elements. Measured results of the circuit showed controllability of the circuit using the MOS resistor.