• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.11
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• pp.1178-1185
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• 2009

In this paper, a wideband ultra-high speed & high purity discrete frequency synthesizer having minimum 2.5 MHz step size was proposed. To achieve fast and wideband operation, discrete frequencies were synthesized by mixing of 3 different pre-synthesized 16 frequencies made from fixed PLL and frequency dividers. Frequencies with discrete 2.5 MHz step were produced in 710~1,610 MHz. The measured hopping response time was 350 nsec average, output level was 21.5 dBm average with 2.65 dB flatness, spurious and harmonics level were suppressed below -60 dBc, and phase noise was -94 dBc/Hz@100 Hz. Also, a new measurement method for synthesizer response time was described.

• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.76-84
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• 1999

For FH/SS communication, We discussed the method of indirect frequency synthesizer in several methods. The problem of sing1e frequency synthesizer using with PLL is a varied coefficient value of damping factor in frequency hopping time, which is caused unstable frequency. So. for stable frequency synthesizer, a coefficient of damping factor must be optimized and synthesized to be removed excessive response time. In this paper, we studied FH using with double loop frequency synthesizer which takes stable frequency. We made up a simulator and had a good performance(real time speed).

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.3
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• pp.128-133
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• 1998

This paper is study on performance analysis of modulator using direct digital frequency synthesizer of Initial Clock Accumulating Method. It has been generally used for PLL or digital frequency synthesizing method to be synthesizd randomly chosen frequency state. In order to improve disadvantage of two methods, we constructed modulator system using DDFS of Initial Clock Accumulating Method. We also confirmed the coherence frequency hopping state and possibility of phase control. The results obtained from the experiments are as follows; First, the synthesized output frequency is proportional to the sampling frequency, according to index, K. Second, the difference of the gain between the basic frequency and the harmonic frequencies was more than 50 [dB], that is, this means facts that is reduced the harmonic frequency factor. Third, coherence frequency hopping state is confirmed by PN code sequence. Here, we confirmed the proposed method cut switching time, this verify facts that is the best characteristic of the frequency hopping. We also verified the fact that the phase varies as the adder is operated set or reset.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.599-607
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• 2004

In this paper, using phase locked loop(PLL) synthesizer, we introduce a novel but simple and low cost frequency modulation(FM) circuit of a flat peak frequency deviation fur modulation signal whose frequency covers from outside to inside of the loop-bandwidth of PLL. The FM circuit was basically designed to compensate an amount of feedback of the loop filter in PLL. The circuit also includes the capability of the adjustment of peak frequency deviation and of blocking the intereference with the loop filter. The designed circuit was successfully implemented and showed the flat frequency deviation as expected in the design. In addition, the novel measurement method of the wideband FM modulation index is suggested verified With the suggest measurement, it can be successfully shown the designed circuit has the expected frequency deviation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1153-1157
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• 2004

This paper describes a new programmable DLL_based frequency synthesizer. Generally, PLLs have been used for frequency synthesis. Inherent fast locking DLLs are also used for frequency synthesis. However, DLL needs a frequency multiplier for various frequencies. A conventional frequency multiplier used in DLL has a restriction in which a multiple is fixed. However, the proposed DLL can generate clocks which are from 6 times to 10 times of the reference clock. Frequency range of the proposed DLL is from 600MHz to 1GHz. The idea has been confirmed by HSPICE simulations in a $0.35-\mu\textrm{m}$ CMOS process.

• The Journal of the Acoustical Society of Korea
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• v.17 no.8
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• pp.103-109
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• 1998

디지털신호의 변조에는 기본적으로 진폭 편이 변조(ASK: Amplitude-Shift Keying), 주파수 편이 변조(FSK: Frequency-Shift Keying), 위상 편이 변조(PSK: Phase-Shift Keying) 등의 세 가지 방법이 있다. 본 논문에서는 표본클록 합성계수 방식에 관한 이론을 고찰하고, 클록초기치 누적방식의 DDFS를 이용하여 위에서 언급한 변조방법을 실현할 수 있는 주파수 도약 대역 확산 통신에 적합한 변조기를 구현하였다. 또한, 합성된 출력주파수 의 정현파형에 대한 스펙트럼 분석과 PN(Pseudo Noise) 부호를 사용한 순시적인 주파수 도 약 상태, 위상제어의 가능성 등을 확인한 결과 실험으로부터 다음과 같은 결과를 얻었다. 첫 째, 합성된 출력주파수는 주파수 Index에 따라 기준주파수에 정확히 정수배가 되며, 둘째, 합성된 정현파형의 스펙트럼으로 기본파와 여러 고조파의 크기를 비교하여 본 결과 50[dB] 이상의 차이가 남으로서 고조파 성분들이 상당히 감소되었음을 확인하였고, 셋째, PN 코드 를 사용하여 순시적인 주파수 도약 상태를 확인하여 본 결과 스위칭 시간이 빠르기 때문에 주파수 도약 특성이 뛰어남을 알 수 있었으며 또한, 누산기의 set/reset 상태를 변화시킴에 따라 위상이 제어됨을 입증하였다.

• The Journal of the Acoustical Society of Korea
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• v.18 no.5
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• pp.52-57
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• 1999

It is very important to design of QAM modulator of high spectral efficiency for high speed data transmission. In this paper, typical 16-QAM modulator is designed by modification design of DDFS(direct digital frequency synthesizer). DDFS generates sinusoidal waveform digitally to the frequency setting word. Phase modulation is accuratly made by control of a generated phase increment value and amplitude modulation is accomplished in the D/A converter output by control of amplitude level. For the suppression of harmonics and glitch, dual-structured DDFS is studied to improve the spurious characteristics. P-Spice is used for design and simulation in mixed mode. Also we can get the satisfactory results of designed 16-QAM modulator from the constellation output.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.3
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• pp.224-238
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• 1987

In the proposed spectrum analyzer, open-loop VCO is replaced with PLL synthesizer incorporating digital frequency synthesizer using modulofunction for measuring precise frequencys. Three different frequency bands and channel spacings are realized by single loop synthesizer through the effective design of the system. The newly designed system with square detection has a good linearity of input range from 10mV to 8.5V, as a result the input sensitivity has been improved up to 500uV. The storage function enables us to analyze not only periodic but also nonperiodic wave-form and zoom-in function expands frequency resolution eight times for the dense spectra.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2409-2418
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• 2013

Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.9
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• pp.536-542
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• 2004

An architecture of direct digital frequency synthesizers (DDFS) is studied in this paper The Direct digital frequency synthesizers (DDFS) provide fast frequency switching with high spectral purity and are widely used in modern spread spectrum wireless communication systems. ROM-based DDFS uses a ROM lookup table to store the amplitude of a sine wave. In this paper, we suggest three new techniques to reduce the ROM size. One new technique uses more number of hierarchical levels in ROM structures. Another techniques use simple interpolation techniques combined with hierarchical ROM structures. A 12 bit sine wave is generated by using these techniques. Experimental results show that the new proposed techniques can reduce the required ROM size by up to 24%, when compared to that of a resent method[1].