• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2444-2450
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• 2011

In this paper, we propose the low fractional spur phase-locked loop(PLL) with multiple phase-frequency detector(PFD). The fractional spurs are suppressed by using a new PFD. The new PFD architecture with two different edge detection methods is used to suppress the fractional spur by limiting a maximum width of the output signals of PFD. The proposed PLL was simulated by HSPICE using a 0.35m CMOS parameters. The simulation results show that the proposed PLL is able to suppress fractional spurs with fast locking.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.809-815
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• 2003

It is very important to get very high switching speed as well as low phase noise of frequency synthesizer in the OFDM/FH communication system. In this paper we compare the phase noises and switching speeds of the conventional PLL and digital hybrid PLL(DH-PLL) frequency synthesizer, also, we investigate the effect of phase noise on the performance of OFDM/FH communication system. DH-PLL has high switching speed property at the cost of circuit complexity and more power consumption. Unlike the conventional PLL in which the phase noise and switching speed have the trade off relationship in respect of loop filter bandwidth, DH-PLL frequency synthesizer can perform fast switching speed and low phase noise simultaneously. Under the condition of same hopping speed requirement, DH-PLL can achieve faster switching speed and lower SNR penalty compared with conventional PLL in the OFDM/FH communication system.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.206-210
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• 2000

본 논문에서는 PLL 주파수 합성기를 이용한 900 MHz 대역의 무선 마이크용 송신기를 설계 및 제작하였다. 위상잡음을 고려한 주파수 합성기는 VCO, Loop Filter 및 RF 중폭부로 구성한 후 HP EEsof ADS ver. 1.3을 이용하여 설계하였다. VCO는 구조가 간단하며 변조가 용이한 직접변조방식을 사용하였으며 Loop Filter는 주파수 합성기의 기준 고조파 성분을 낮추기 위해 수동 3차 필터를 사용하였다. 주파수 대역 928.125 MHz～929.875 MHz 내에서 채널간격 125 kHz를 갖으며 15개의 채널이 되도록 분주비를 설정한 주파수 합성기는 제작 결과, 송신기 출력 9.3 dBm과 위상잡음이 100 kHz에서 -113 dBc/Hz 이하의 위상잡음 특성을 나타내었고 불요주파수 특성은 -80 dBc 이하의 특성을 나타내었다.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.2017-2019
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• 2004

본 논문에서는 S/C-밴드(2${\sim}$8GHz)에서 동작하는 초광대역 주파수 합성기를 설계하였다. 먼저 S-밴드(2-4GHz) 광대역 전압제어발진기를 가지고 획득시간을 단축하기 위한 연산 증폭기를 사용한 DA변환기와 능동루프 필터(Active Loop Filter)로 구성된 S-밴드 주파수 합성기를 설계하였다. 그리고 주파수 체배기, SPDT RF 스위치를 통합하여 최종적으로 S/C-밴드 초광대역 주파수 합성기를 설계하였다. 제작된 주파수 합성기는 200kHz 비교주파수에서 위상잡음은 100kHz 옵셋 주파수에서 -92dBc/Hz이하, 불요주파수 특성은 -62.33dBc 이하, 획득시간은 1.3ms 이하로 측정되었다.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.252-254
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• 2009

본 논문에서는 저고도 탐지레이다 센서체계의 주파수 합성기는 송수신 장치의 기준 주파수원으로 이용될 국부 발진 주파수들을 생성해 내는 주파수 합성부에 대해 설명되었다. 주파수 합성기의 성능을 평가하기위하여 각 주파수 원들의 위상잡음 특성과 주파수 합성기의 스위칭 시간을 신호 혼합기를 이용하여 측정 하였으며, 그 결과 설계 시 제시한 30(usec)이하인 약18usec의 스위칭 시간이 대부분을 차지함을 알 수 있었다. 주파수 합성기에서 생성된 최종 출력 주파수는 저고도 탐지 레이다의 송수신 장치의 국부발진 주파수로 이용되므로 출력 레벨의 flatness를 측정하여 분석한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2B
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• pp.151-159
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• 2002

Frequency synthesizer is an essential part for developing high speed frequency hopping radio. A high speed synthesizer using DDS driven PLL technique is designed and implemented for a X-band portable satellite terminal. It generates transmitter and receiver frequency ranging 6600∼7100MHz and 6140∼6640MHz, respectively by using 102.4MHz local oscillator, Its lock time is below 15 $\mu$sec and Its phase noise is below -754dBc at 1KHz offset Sequency.

• Journal of IKEEE
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• v.17 no.1
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• pp.16-21
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• 2013

Recently, frequency synthesizers are being designed in two ways narrow-band loop or dual-loop for wide-band to reduce the phase noise. However, dual-loop has the disadvantage of center frequency mismatch and requiring an extra loop. In this paper, we propose a new structure that supports a range of 800Mhz ~ 3Ghz with multiple control of the single-loop frequency synthesizer without another loop. The control voltage of the VCO(coarse, fine) will be fixed, and finally the VCO will have a low Kvco. The frequency synthesizer is simulated using UMC $0.11{\mu}m$ process, proposed frequency synthesizer can be used in a variety of applications in the future.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.12
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• pp.1251-1257
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• 2014

In this paper, a 6~13 GHz ultra high speed frequency synthesizer having minimum 30 kHz step size and minimum 500 ns frequency settling time is proposed. In order to obtain fast settling time, fine resolution, and good phase noise performance, wideband output frequencies were synthesized based on DDS(Direct Digital Synthesizer) and analog direct frequency synthesis technology. The phase noise performance of wideband frequency synthesizer was estimated by the superposition theory and its results were compared with measured ones. The measured frequency settling time was below 500 ns, phase noise was below -106 dBc @ 10 kHz at 13 GHz, and frequency accuracy was measured below ${\pm}2kHz$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.5
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• pp.879-886
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• 2003

Agile frequency synthesizers are the common device used for commandable, wide-band frequency hopping in frequency-hopped (FH) communications. In this paper, synthesizer phase transient effect and its compensation methods in an FH/FSK(Frequency Hopped Frequency Shift Keying) system are studied. Models for these analysis are developed and resulting performance degradations are computed. The basic PLL is difficult to implement for fast frequency hopping in narrowband radio communication systems. To solve this problem, digital frequency synthesizer/CPM (Continuous Phase Modulation)modulator is proposed. And it's performance is analyzed theoretically. The analysis show that fast frequency hopping is possible in frequency hopping system that use digital frequency synthesizer/CPM modulator.

• Journal of Advanced Navigation Technology
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• v.2 no.1
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• pp.22-33
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• 1998

In the coherent-on-receiver radar system using the magnetron source, frequency synthesizer is employed as a STALO(Stable Local Oscillator) to keep the intermediate frequency stable. In this paper, X-band(8.4GHz~9.7GHz) single loop frequency synthesizer is designed and implemented by an indirect frequency synthesis technique. Phase comparison is performed by a digital PLL(Phase-Locked Loop) chip and the loop filter is designed for the low phase noise. The effects of loop component characteristics on the output phase noise are analyzed for single loop structures, and the calculated results are compared with the measured data.