• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.586-592
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• 2006

In this paper, a novel detection method called the joint multiple frequency cell (JMFC) detection is addressed for spread spectrum code acquisition in the presence of residual Doppler frequency offset (RDFO). When the RDFO exists, the correlation peak used for detection during the acquisition process is split into several lower neighboring peaks, resulting in severe degradation in the detection performance, and consequently, in the overall acquisition performance. In the JMFC detection, a decision variable for detection is formed by combining several consecutive correlator outputs, so that the reduction in the correlation value due to the RDFO can be alleviated. Numerical results show that the proposed scheme can offer better detection performance over the conventional scheme based on the cell-by-cell detection.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.828-835
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• 2001

Novel bipolar transresistance amplifier(TRA) and its offset-compensated TRA for high-performance current-mode signal processing are described. The TRA consist of two current follower for a current inputs, a current summer for the current-difference, a resistor for the current to voltage converter, and a voltage follower for the voltage output. The offset-compensated TRA adopts diode-connected npn and pnp transistor to reduce offset voltage in the TRA. The simulation results show that the TRA has impedance of 0.5 Ω at the input and the output terminal. The offset voltages at these terminals is 40 mV The offset-compensated TRA has the offset voltage of 1.1 mV and the impedance of 0.25 Ω. The 3-dB cutoff frequency is 40 MHz for the two TRA＇s when used as a current to voltage converter with unit-gain transresistance. The power dissipation is 11.25 mW.

• Journal of Broadcast Engineering
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• v.16 no.5
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• pp.793-796
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• 2011

H.264/AVC compresses video data by applying DCT transform, quantization and entropy coding processes to the residual signal obtained by inter/intra prediction. This paper proposes a method enhancing an existing DC offset adjustment technology which uses information of neighboring blocks to reduce residual information for improving coding efficiency. DC offset information is not sent over bitstreams, but calculated in the same way both in the decoder and in the encoder. Experimental results show that the proposed method enhances coding efficiency by 0.25% in average BD-Rate compared to H.264/AVC and gives better or worse coding efficiency compared to the existing DC offset method depending on video sequences with coding efficiency degradation by 0.09% in average BD-Rate. This experimental results also show that further coding efficiency improvement is possible by applying the proposed method adaptively to slice or macroblock coding units.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.10
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• pp.65-72
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• 2000

In this paper, we propose an efficient technique to minimize the input offset of a dynamic latch comparator. We analyzed offset due to charge injection mismatching and unwanted positive feedback during sampling phase. The last one was only considered in the previous works. Based on the analysis, we proposed a modified dynamic latch with initialization switch. The proposed circuit was simulated using 0.65${\mu}m$ CMOS process parameter with 5v supply. The simulation results showed that the input offset is less than 5mV ant 200MHz sampling frequency and the input offset is improved about 80% compared with previous work in $5k{\Omega}$ input resistance.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.4
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• pp.729-736
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• 2018

Due to the frequency offset, interchannel interference (ICI) is occurred in the received symbols of the orthogonal frequency division multiplexing (OFDM) systems. The ICI self-cancellation (ICI-SC) technique appropriately adjusts the subchannel signal assignment of the OFDM symbols, thereby canceling the interference caused by other subchannels. The conventional adjacent symbol repetition (ASR) method can reduce the interference caused by remote subchannels. However, it may not mitigate or even increases the ICI produced by some nearest subchannels. To solve the problem, a new ASR based ICI-SC technique is proposed and its performance is analyzed in this paper. Here, a t-parameter obtained by the interference coefficients of 3 successive subchannels is applied. As a result, the proposed method has the same capability to reduce the influence of remote subchannels. However, it can reduce the ICI caused by the nearest subchannels significantly.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.152-159
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• 2016

This paper describes an offset and 1/f noise cancellation technique based hall sensor signal processor. The hall sensor outputs a hall voltage from the input magnetic field, which direction is orthogonal to hall plate. The two major elements to complete the hall sensor operation are: the one is a hall sensor to generate hall voltage from input magentic field, and the other one is a hall signal process system to cancel the offset and 1/f noise of hall signal. The proposed hall sensor splits the hall signal and unwanted signals(i.e. offset and 1/f noise) using a spinning current biasing technique and chopper stabilizer. The hall signal converted to 100 kHz and unwanted signals stay around DC frequency pass through chopper stabilizer. The unwanted signals are bloked by highpass filter which, 60 kHz cut off freqyency. Therefore only pure hall signal is enter the ADC(analog to dogital converter) for digitalize. The hall signal and unwanted signal at the output of an amplifer and highpass filter, which increase the power level of hall signal and cancel the unwanted signals are -53.9 dBm @ 100 kHz and -101.3 dBm @ 10 kHz. The ADC output of hall sensor signal process system has -5.0 dBm hall signal at 100 kHz frequency and -55.0 dBm unwanted signals at 10 kHz frequency.

• Journal of Advanced Navigation Technology
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• v.11 no.4
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• pp.394-400
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• 2007

We induced the optimal values of optical phase conjugator (OPC) position and dispersion coefficients of fiber sections depending on frequency chirp, which is substantially generated in optical signal by optical modulator and affects the transmission performances. In order to investigate the relation of optimal parameters with various frequency chirp, in this paper, positive(down) chirp, chirp-free and positive(up) chirp are assumed in 40 Gbps ${\times}$ 16 channels WDM transmission system of NRZ format with extinction ratio of 10 dB, which are the worst system parameters in the factor affecting system performance. It is confirmed that the OPC position offset and dispersion offsets between both fiber sections are more increased as frequency chirp become larger. It is also confirmed that the effect of the induced values on the compensation of WDM channels with negative frequency chirp is better than WDM channels with positive frequency chirp.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.57-63
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• 2016

This paper describes implementation of the RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4g SUN sensor node transceiver modules. Design of the each module like VCO, prescaler, 1/N divider, ${\Delta}-{\Sigma}$ modulator, and common circuits of the PLL has been optimized to obtain high speed and low noise performance. Especially, the VCO has been designed with NP core structure and 13 steps cap-bank to get high speed, low noise, and wide band tuning range. The output frequencies of the implemented synthesizer is 1483MHz~2017MHz, the phase noise of the synthesizer is -98.63dBc/Hz at 100KHz offset and -122.05dBc/Hz at 1MHz offset.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.42-49
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• 2016

In this paper, we design and fabricate an instantaneous frequency measurement receiver with a frequency resolution of 125 MHz which detects and measures continuous signals in 4~6 GHz using path difference of delay lines. The receiver has a 4-bit configuration and consists of power dividers, delay lines, power combiners, power detectors, voltage comparator circuits and so on. The accuracy of the instantaneous frequency measurement is improved by applying offset voltage compensation to the comparator circuits to compensate the frequency-dependent path loss of the delay line and the frequency dependence of power detection.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.4
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• pp.11-17
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• 2001

In this paper, we propose a polarity decision carrier recovery algorithm for high order QAM(Quadrature Amplitude Modulation), which has robust and large frequency acquisition performance in the high order QAM modem. The proposed polarity decision PD(Phase Detector) output and its variance characteristic are mathematically derived and the simulation results are compared with conventional DD(Decision-Directed) method. While the conventional DD algorithm has linear range of $3.5^{\circ}{\sim}3.5^{\circ}$, the proposed polarity decision PD algorithm has linear range as large as $-36^{\circ}{\sim}36^{\circ}$ at ${\gamma}-17.9$. The conventional DD algorithm can only acquire offsets less than ${\pm}10\;KHz$ in the case of the 256 QAM while an analog front-end circuit generally can reduce the carrier-frequency offset down to only ${\pm}100\;KHz$. Thus, in this case additional AFC or phase detection circuit for carrier recovery is required. But by adopting the proposed polarity decision algorithm, we can find the system can acquire up to ${\pm}300\;KHz$at SNR = 30dB without aided circuit.