• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.49-54
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• 2009

This paper describes implementation of the 1.9GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma }-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.2{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.1{\times}0.4mm^2$. The test results show that there is no special spurs except -63.06dB of the 6MHz reference spurs in the PLL circuitry. There is good phase noise performance like -116.17dBc/Hz in 1MHz offset frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.3
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• pp.401-408
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• 2001

This paper shows the design, fabrication and performance analysis of VCO which plays a major role in 5.8 GHz RF module for ITS. The design specifications of the VCO are determined on the basis of 5.8 GHz RF modul performance requirements. The design parameters are optimized through ADS simulation tool. The operating characteristic and performance analysis of the implemented VCO based on the design parameters are accomplished. The frequency variations according to the voltage change(0 ~5 V) of varactor diode are from 5.42 GHz to 5.518 GHz and the power level is 6.5 dBm. The second harmonic suppression are -21.5 dBc at 5.51 GHz and the phase noise characteristics are -83.81 dBc at 10 kHz offset frequency. The implemented VCO is available to not only DSRC and also, 5.8 GHz other systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.325-336
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• 2013

FlashLinQ, one of the typical D2D communication systems developed by Qualcomm, considers a single-tone communication based distributed channel-aware link scheduling method to realize the link scheduling process with low control overheads. However, considering the frequency selective fading effect of practical multi-path channel, the single-tone based SIR estimation causes a critical scheduling error problem because the received single-tone signal has quite different channel gain at each sub-carrier location. In order to overcome this problem, we propose a novel link scheduling method based on CAZAC (Constant Amplitude Zero Auto-Correlation) sequence for D2D communication system. In the proposed method, each link has a unique offset value set for the generation of CAZAC sequences. CAZAC sequences with the cyclic offsets are transmitted using multiple sub-blocks in the entire bandwidth, and then each device can obtain nearly full-band SIR using a good cyclic cross-correlation property of CAZAC sequence.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.539-546
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• 2007

In this paper, a 3-D EM simulation methodology for on-chip spiral inductor analysis has provided and it is shown that the methodology can be adapted to the highly predictable design for CMOS VCO. LC-resonator type VCO have fabricated by using standard 0.25 um CMOS process. And the LC VCO layout case which has pattern ground shielded inductors and the other layout case which has no pattern grounded inductors were fabricated for the verification of their effects on the VCO's phase noise by reducing the Q-factor of inductors. Fabricated VCO has 3.094 GHz, -12.15 dBm output at the tuning voltage of 2.5 V, and from the simulation, Q-factor of the pattern grounded inductor has increased 8% at 3 GHz, and from the measurement results, the phase noise has reduced by 9 dB at the 3 MHz off-set frequency for the pattern grounded inductor layout case.

• Journal of Navigation and Port Research
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• v.26 no.2
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• pp.215-220
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• 2002

In this paper, the 100 watt unit ower amplifier using temperature independent biasing for DTV (Digital Television) repeater application is designed and fabricated. The DC operation point of this unit power amplifier at temperature variation from $20^{\circ}C$ to $100^{\circ}C$ is fixed by active bias circuit. The variation of current consumption in the 100 watt unit power amplifier has an excellent characteristics of less than 0.6A. The implemented unit power amplifier has the gain over 12dB, the gain flatness of less than 0.5dB and input and output return, loss of than 15dB over the DTV repeater frequency range (470~806MHz). This unit power amplifier yields intermodulation distortion(IMD) of more than 32dBc at 2MHz offset, which satisfies the IMD at output power of 100 watt (50dBm).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2719-2730
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• 2009

In this paper, we implement the measurement functionality for performance measurements of EDGE (Enhanced Data Rates for GSM Evolution) terminal by using software. Generally speaking, the receiving algorithms in normal MODEM cannot be used directly to a measurement system due to the lack of accuracy. Therefore, we propose a new receiver algorithm for precise EDGE signal measurements. In the proposed algorithm, 2-stage (coarse stage, fine stage) parameters estimation (symbol-timing, frequency offset, carrier phase) scheme is used. To improve the estimation accuracy, we increase the number of the received signal samples by interpolation. The proposed EDGE signal measurement algorithm can be used for verifying the hardware measurement system, and also can be used for the commercial systems through software optimization.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.1
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• pp.65-73
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• 2007

This paper presents an on-line correction method of current measurement errors for a pure-integration-based flux estimation down to 1-Hz stator frequency. An observer-based approach is taken as one possible solution of eliminating the dc offset and the negative sequence component of unbalanced gains in the synchronous coordinate. At the same time, the positive sequence component estimation is performed by creating an error signal between a motor model reference and an estimated q-axis rotor flux established by a permanent magnet (PM) in the synchronous coordinate. The compensator utilizes a PI controller that controls the error signal to zero. The proposed technique further contains a residual error compensator to completely eliminate miscellaneous disturbances in the estimated flux. The developed algorithm has been implemented on a 1.1-kW permanent magnet synchronous motor (PMSM) drive to confirm the effectiveness of the proposed scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.9
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• pp.2369-2378
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• 2009

In this paper, we implement measurement functionality for performance measurement of the GSM (Global System for Mobile Communication) terminal by using software. Generally speaking, the receiving algorithms in normal modems cannot be used directly to the measurement system due to the lack of the algorithm accuracy. In this paper, we propose the new receiver algorithm for precise GSM signal measurements. In the receiving algorithm, 2-stage (coarse stage, fine stage) parameters estimation (symbol-timing, frequency offset, carrier phase) scheme is used. To improve the estimation accuracy, we increase the number of the received signal samples by interpolation. The proposed GSM signal measurement algorithm can be used for verifying the hardware measurement system. In addition, the proposed algorithm can be used for the commercial system through code execution speed optimization.

• Journal of Advanced Navigation Technology
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• v.17 no.6
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• pp.705-711
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• 2013

In this paper, we present a low-complexity non-coherent demodulation algorithm and hardware architecture for LR-WPAN systems which can support the variable data rate for various applications. The need for LR-WPAN systems that can support the variable data rate is increasing due to the emergence of various sensor applications. Since the existing symbol based double correlation (SBDC) algorithm requires the increase of complexity to support the variable data rate, we propose the sample based double correlation (SPDC) algorithm which can be implemented without the increase of complexity. The proposed non-coherent demodulator was designed by verilog HDL and implemented with FPGA prototype board.