• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.271-274
• /
• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.3
• /
• pp.399-405
• /
• 2011

In this paper, we present the design of Q-band LC VCO and injection locking buffer for 77 GHz automotive radar sensor using 130 nm RF CMOS process. To improve the phase noise characteristic of LC tank, the transmission line is used. The negative resistance by the active device cross-coupled pair of buffer is used for high output power, with or without oscillation of buffer. The measured phase noise is -102 dBc/Hz at 1 MHz offset frequency and tuning range is 34.53~35.07 GHz. The output power is higher than 4.1 dBm over entire tuning range. The fabricated chip size is $510{\times}130\;um^2$. The power consumption of LC VCO is 10.8 mW and injection locking buffer is 50.4 mW from 1.2 V supply.

• The Journal of Engineering Geology
• /
• v.31 no.4
• /
• pp.603-620
• /
• 2021

A land nodal seismic system was employed to acquire seismic reflection data using stand-alone cable-free receivers in a land-river area. Acquiring reliable data using this technology is very cost effective, as it avoids topographic problems in the deployment and collection of receivers. The land nodal airgun system deployed on the mouth of the Hyungsan River (in Pohang, Gyeongsangbuk Province) used airgun sources in the river and receivers on the riverbank, with subparallel source and receiver lines, approximately 120 m-spaced. Seismic data collected on the riverbank are characterized by a low signal-to-noise (S/N) and inconsistent reflection events. Most of the events are represented by hyperbola in the field records, including direct waves, guided waves, air waves, and Scholte surface waves, in contrast to the straight lines in the data collected conventionally where source and receiver lines are coincident. The processing strategy included enhancing the signal behind the low-frequency large-amplitude noise with a cascaded application of bandpass and f-k filters for the attenuation of air waves. Static time delays caused by the cross-offset distance between sources and receivers are corrected, with a focus on mapping the shallow reflections obscured by guided wave and air wave noise. A new time-distance equation and curve for direct and air waves are suggested for the correction of the static time delay caused by the cross-offset between source and receiver. Investigation of the minimum cross-offset gathers shows well-aligned shallow reflections around 200 ms after time-shift correction. This time-delay static correction based on the direct wave is found essential to improving the data from parallel source and receiver lines. Data acquisition and processing strategies developed in this study for land nodal airgun seismic systems will be readily applicable to seismic data from land-sea areas when high-resolution signal data becomes available in the future for investigation of shallow gas reservoirs, faults, and engineering designs for the development of coastal areas.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.05a
• /
• pp.88-90
• /
• 2012

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.16 no.6 s.97
• /
• pp.603-614
• /
• 2005

In this paper, digital ultra-narrowband Walky-Talky using direct conversion method for CQPSK modulation scheme is implemented with satisfying the requirements of APCO P25. RF transceiver design and implementation scheme that minimize the influence of DC-offset and AC-coupling at ultra-narrowband is proposed. This scheme also minimizes the influence of nonlinear characteristic at power amplifier fir CQPSK modulation method. Test results of full system including DSP module and direct conversion RF transceiver show that FCC emission mask at 36.8 dBm PEP meets the standard requirements. The characteristic of receiver AGC by PWM control signal is linear at 40 dB dynamic range and voice communication at input power level of -116 dBm is successful. Also it is verified that the performance of BER versus frequency offset and versus SNR meets the standard requirements.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.7 no.4
• /
• pp.715-720
• /
• 2012

This study presents a hybrid balanced voltage controlled oscillator (VCO) circuit which is suitable for low phase noise operation at sub-1V supply voltages. Half circuits of the proposed VCO use the varactor-integrated feedback capacitors in their respective circuit. The varactor-integrated feedback capacitors further increase the negative resistance of the equivalent tank thereby ensuring stable start-up of oscillation even at the sub-1V supply voltage. In addition, this work theoretically analyses the phenomenon of the increase of the negative resistance. Simulation results using a $0.18{\mu}m$ RF CMOS technology exhibit the phase noises of -122.4 to -125.5.8 dBc/Hz at 1 MHz offset from oscillation frequency of 4.87 GHz over the supply voltages of 0.6 through 0.9 V.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.2
• /
• pp.391-396
• /
• 2013

In this paper, for HEVC decoding, an SAO hardware design with less processing time and reduced area is proposed. The proposed SAO hardware architecture introduces the design processing $8{\times}8$ CU to reduce the hardware area and uses internal registers to support $64{\times}64$ CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC $0.18{\mu}m$ library, the gate area is 30.7k and the maximum frequency is 250MHz. The proposed SAO hardware architecture can process the decode of a macroblock in 64 cycles.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.2
• /
• pp.414-422
• /
• 2013

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

• Journal of Satellite, Information and Communications
• /
• v.10 no.2
• /
• pp.109-114
• /
• 2015

Frame synchronization is achieved by correlation between received symbols and a preamble pattern which is periodically appended at a frame header. In this paper, we deal with a frame detection method complaint with satellite-based DVB-S2 system. In DVB-S2, frame synchronization is performed under the low signal-to-noise ratio(SNR), a large frequency offset which can be up to 20% of a symbol transmission rate and unknown modulation schemes ranging from QPSK to 32-APSK. In this environment, we propose a method combining differential correlation based on SOF and PLSC with an accumulated correlation method for the detection of frame structures. In addition, detection performances about mean acquisition time(MAT) and detection error probability are evaluated via computer simulations.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.8
• /
• pp.3053-3059
• /
• 2010

In DS-CDMA method, Mobile Stations own jointly one radio channel and are made to use a PN code (Pseudo-Noise Code) for the purpose of minimize interference. However, corelation value of PN code is one when time delay is zero but the corelation value is 1 / N when time delay is not 0. Therefore corelation characteristic does not fully attained. As a result, when the user increase, the performance degradation and system capacity problem will be able to occur by interference among users. In this paper, the PN code has ideally self corelation. It was proved that PN code could depress interference from other users in multiple access system.