• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2017.06a
• /
• pp.81-82
• /
• 2017

본 논문에서는 PSNR 을 높이도록 최적화된 HEVC 의 율-왜곡 최적화(RDO)를 MS-SSIM 를 높이도록 하여 RDO 를 수행 하도록 한다. 구현 방법으로는 MS-SSIM 도출 방법과 비슷하도록 원본과 4 단계의 저역 통과 필터(LPF)를 통과한 결과에 대한 DCT(Discrete Cosine Transform) 를 수행하고 그 AC 계수의 비율로 lagrange multiplier(${\lambda}$)를 수정하는 방식이다. AC 계수 비율과 MS-SSIM 에서 도출 된 가중치, LPF 특성 등에 따라 새롭게 각 스케일의 가중치를 결정하여 최종적으로 ${\lambda}$ 가중치를 결정하여 그 결과를 바탕으로 RDO 를 수행한다. 시뮬레이션을 통해 제안의 방법과 HEVC reference software 의 BD-rate 계산 결과 7%의 PNSR, -13.2%의 MS-SSIM 를 얻을 수 있었고 이에 따라 주관적 화질을 개선했다고 할 수 있다.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.775-776
• /
• 2008

본 논문은 WLAN 환경에서 웨이블릿과 신경망을 사용한 실내 위치인식 방법을 제안한다. 제안한 방법의 기본적인 아이디어는 경제적이면서 효율적인 방법으로써 실내에 설치된 무선 AP들로부터 수신된 신호들의 수신세기로부터 비교적 정확하게 위치를 추정하는 연구이다. 일반적으로 무선 신호는 주위 환경 및 건물 구조적 요인에 의해 수신세기가 더해지거나 감해지는 현상이 발생함으로써 수신된 각 신호세기로부터 신호 잡음과 오류에 강인하고 시간과 주파수 도메인의 정보 표현이 가능하며 각 신호세기들간의 구별성을 갖는 특징값 획득이 필요하다. 제안 방법에서는 웨이블릿 변환을 이용하여 수신된 신호로부터 중복 데이터와 잡음에 민감하게 반응하지 않는 특징값을 획득하고, 수신신호 전역 및 지역적 특징의 표현이 가능한 신경망을 사용하여 실내위치인식 방법은 제안한다. 실험 결과 실내위치 인식률이 94 % 이상 제시하였다.

• Proceedings of the KIEE Conference
• /
• 2002.07d
• /
• pp.2513-2514
• /
• 2002

근육이나 신경질환의 진단을 위해 사용되고 있는 근전도 신호를 홈 오토메이션 분야에 구현하여 일반인이나 기타 기능성 장애를 호소하는 사람들에게 보다 효율적으로 가전기기들을 제어할 수 있는 방법을 제시하고자 한다. 해당 동작과 관련된 신호 패턴을 구분하기 위해 주파수 도메인에서 FFT 방법을 이용하고, FFT에 의해 분류된 동작을 론웍스 상에 연결된 가전기기들과 연결시켜 줌으로써 손쉽게 홈 오토메이션을 구현할 수 있다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2017.11a
• /
• pp.954-956
• /
• 2017

본 연구에서는 X-선 영상을 이용한 비산란 그리드의 검사 자동화 시스템에서, 결함후보 ROI에 대한 판단정확도를 향상시킬 수 있는 최적영상 획득을 위한 임계치결정 기법을 제안한다. 주파수 도메인에서 영상히스토그램을 분석 및 재구성한 후 최적임계치의 결정에 필요한 요소를 추출하며, 재구성 히스토그램으로부터 영상패턴을 판단하여 각 유형에 따른 최적 임계치를 결정한다. 50개의 영상에 적용한 실험 결과 제안된 방법은 4.8/5.0의 성능 (Inter-class correlation, ICC: 0.985, 95% CI, p-value<0.05)을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.11
• /
• pp.9-16
• /
• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Korean Journal of Remote Sensing
• /
• v.26 no.5
• /
• pp.581-591
• /
• 2010

In this paper, we proposed a new wavelet-based image fusion algorithm, which has advantages in both frequency and spatial domains for signal analysis. The developed algorithm compares the ratio of SAR image signal to optical image signal and assigns the SAR image signal to the fused image if the ratio is larger than a predefined threshold value. If the ratio is smaller than the threshold value, the fused image signal is determined by a weighted sum of optical and SAR image signal. The fusion rules consider the ratio of SAR image signal to optical image signal, image gradient and local variance of each image signal. We evaluated the proposed algorithm using Ikonos and TerraSAR-X satellite images. The proposed method showed better performance than the conventional methods which take only relatively strong SAR image signals in the fused image, in terms of entropy, image clarity, spatial frequency and speckle index.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.1
• /
• pp.84-89
• /
• 2019

JPEG is a most widely used standard image compression technology. This research introduces the JPEG image compression algorithm and describes each step in the compression and decompression. Image compression is the application of data compression on digital images. The DCT (discrete cosine transform) is a technique for converting a time domain to a frequency domain. First, the image is divided into 8 by 8 pixel blocks. Second, working from top to bottom left to right, the DCT is applied to each block. Third, each block is compressed through quantization. Fourth, the matrix of compressed blocks that make up the image is stored in a greatly reduced amount of space. Finally if desired, the image is reconstructed through decompression, a process using IDCT (inverse discrete cosine transform). The purpose of this research is to review all the processes of image compression / decompression using the discrete cosine transform method.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.12
• /
• pp.1882-1889
• /
• 2021

This paper describes a high-performance hardware implementation of modular multiplication used as a core operation in elliptic curve cryptography. A 521-bit high-performance modular multiplier for NIST P-521 curve was designed by adopting 3-way Toom-Cook integer multiplication and fast reduction algorithm. Considering the property of the 3-way Toom-Cook algorithm in which the result of integer multiplication is multiplied by 1/3, modular multiplication was implemented on the Toom-Cook domain where the operands were multiplied by 3. The modular multiplier was implemented in the xczu7ev FPGA device to verify its hardware operation, and hardware resources of 69,958 LUTs, 4,991 flip-flops, and 101 DSP blocks were used. The maximum operating frequency on the Zynq7 FPGA device was 50 MHz, and it was estimated that about 4.16 million modular multiplications per second could be achieved.

• Journal of Broadcast Engineering
• /
• v.22 no.1
• /
• pp.28-41
• /
• 2017

In this paper, the fast encoding algorithm in High Efficiency Video Coding (HEVC) encoder was studied. For the encoding efficiency, the current HEVC reference software is divided the input image into Coding Tree Unit (CTU). then, it should be re-divided into CU up to maximum depth in form of quad-tree for RDO (Rate-Distortion Optimization) in encoding precess. But, it is one of the reason why complexity is high in the encoding precess. In this paper, to reduce the high complexity in the encoding process, it proposed the method by determining the maximum depth of the CU using a hierarchical clustering at the pre-processing. The hierarchical clustering results represented an average combination of motion vectors (MV) on neighboring blocks. Experimental results showed that the proposed method could achieve an average of 16% time saving with minimal BD-rate loss at 1080p video resolution. When combined the previous fast algorithm, the proposed method could achieve an average 45.13% time saving with 1.84% BD-rate loss.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.43 no.4 s.310
• /
• pp.87-95
• /
• 2006

In this paper, we propose a novel feature extraction method for face recognition, based on Discrete Cosine Transform (DCT), Energy Probability (EP), and Linear Discriminant Analysis (LDA). We define an energy probability as magnitude of effective information and it is used to create a frequency mask in OCT domain. The feature extraction method consists of three steps; i) the spatial domain of face images is transformed into the frequency domain called OCT domain; ii) energy property is applied on DCT domain that acquire from face image for the purpose of dimension reduction of data and optimization of valid information; iii) in order to obtain the most significant and invariant feature of face images, LDA is applied to the data extracted using frequency mask. In experiments, the recognition rate is 96.8% in ETRI database and 100% in ORL database. The proposed method has been shown improvements on the dimension reduction of feature space and the face recognition over the previously proposed methods.