• The KIPS Transactions:PartA
• /
• v.12A no.7 s.97
• /
• pp.571-582
• /
• 2005

NAND flash memory has advantages of non-volatility, little power consumption and fast access time. However, it suffers from inability that dose not provide to update-in-place and the erase cycle is limited. Moreover, the unit of read and write operations is a page. A NAND flash file system called YAFFS has been proposed. But YAFFS has several problems to be addressed. In this paper, the Reliable Flash File System(RFFS) for NAND flash memory is designed and evaluated. In designing a file system the following four issues must be considered in particular for the design: (i) to minimize a repairing time when the system fault occurs, (ii) to balance the number of block erase operations by offering wear leveling policy, and (iii) to reduce turnaround time of memory operations by reducing the amount of data written. We demonstrate and evaluate the performance of the proposed schemes.

• Journal of KIISE:Databases
• /
• v.35 no.4
• /
• pp.319-332
• /
• 2008

Data cube, which is multi-dimensional data model, have been successfully applied in many cases of multi-dimensional data analysis, and is still being researched to be applied in data stream analysis. Data stream is being generated in real-time, incessant, immense, and volatile manner. The distribution characteristics of data arc changing rapidly due to those characteristics, so the primary rule of handling data stream is to check once and dispose it. For those characteristics, users are more interested in high support attribute values observed rather than the entire attribute values over data streams. This paper propose dynamic data cube for applying data cube to data stream environment. Dynamic data cube specify user's interested area by the support ratio of attribute value, and dynamically manage the attribute values by grouping each other. By doing this it reduce the memory usage and process time. And it can efficiently shows or emphasize user's interested area by increasing the granularity for attributes that have higher support. We perform experiments to verify how efficiently dynamic data cube works in limited memory usage.

• KIISE Transactions on Computing Practices
• /
• v.21 no.1
• /
• pp.88-93
• /
• 2015

In modern computer systems, DRAM is commonly used as main memory due to its low read/write latency and high endurance. However, DRAM is volatile memory that requires periodic power supply (i.e., memory refresh) to sustain the data stored in it. On the other hand, PCM is a promising candidate for replacement of DRAM because it is non-volatile memory, which could sustain the stored data without memory refresh. PCM is also available for byte-addressable access and in-place update. However, PCM is unsuitable for using main memory of a computer system because it has two limitations: high read/write latency and low endurance. To take the advantage of both DRAM and PCM, a hybrid main memory, which consists of DRAM and PCM, has been suggested and actively studied. In this paper, we propose a novel page replacement algorithm for hybrid main memory. To cope with the weaknesses of PCM, our scheme focuses on reducing the number of PCM writes in the hybrid main memory. Experimental results shows that our proposed page replacement algorithm reduces the number of PCM writes by up to 80.5% compared with the other page replacement algorithms.

• Journal of KIISE:Computer Systems and Theory
• /
• v.27 no.6
• /
• pp.567-582
• /
• 2000

We propose a new way of managing flash memory space for flash memory-specific file system based on log-structured file system. Flash memory has attractive features such as non-volatility, and fast I/O speed, but it also suffers from inability to update in place and limited usage cycles. These drawbacks require many changes to conventional storage (file) management techniques. Our focus is on lowering cleaning cost and evenly utilizing flash memory cells while maintaining a balance between the two often-conflicting goals. The proposed cleaning method performs well especially when storage utilization and the degree of locality are high. The cleaning efficiency is enhanced by dynamically separating cold data and non-cold data. The second goal, cycle-leveling is achieved to the degree where the maximum difference between erase cycles is below the error range of the hardware. Simulation results show that the proposed method has significant benefit over naxve methods: maximum of 35% reduction in cleaning cost with even spreading writes across segments.

• Journal of the Korea Society of Computer and Information
• /
• v.25 no.2
• /
• pp.21-29
• /
• 2020

The use of NAND flash memory is continuously increased with the demand of mobile data in the IT industry environment. However, the erase operations in flash memory require longer latency and higher power consumption, resulting in the limited lifetime for each cell. Therefore, frequent write/erase operations reduce the performance and the lifetime of the flash memory. In order to solve this problem, management techniques for improving the performance of flash based storage by reducing write and erase operations of flash memory with using disk buffers have been studied. In this paper, we propose a CPWL to minimized the number of write operations. It is a disk buffer management that separates read and write pages according to the characteristics of the buffer memory access patterns. This technique increases the lifespan of the flash memory and decreases an energy consumption by reducing the number of writes by arranging pages according to the characteristics of buffer memory access mode of requested pages.

• Journal of the Korea Society of Computer and Information
• /
• v.25 no.6
• /
• pp.99-107
• /
• 2020

In this paper, we analyze the characteristics of mobile cache, which is used to improve the data access speed when executing applications on mobile devices, and verify the importance of mobile cache through a cache data access experiment. The mobile device market has grown at a fast pace over the past decade; however, battery limitations and size, price considerations restrict the usage of fast hardware. Thus, their performance are supplemented by using a memory buffer structure such as the cache memory. The analysis mainly focuses on cache size, hierarchical structure of cache, cache replacement policy, and the effect these features has on mobile performance. For the experimental data, we applied a data set from a microprocessor system study, originally used to test the cache performance. In the experimental results, the average data access speed on a mobile device showed a performance improvement of up to 10 times with the presence of cache memory than without. Accordingly, the cache memory was helpful for the performance improvement of a mobile device when the specifications were identical.

• KIPS Transactions on Computer and Communication Systems
• /
• v.10 no.5
• /
• pp.123-136
• /
• 2021

RPC (Remote Procedure Call)-based Graphics Processing Unit (GPU) virtualization technology is one of the technologies for sharing GPUs with multiple user virtual machines. However, in a cloud environment, unlike CPU or memory, general GPUs do not provide a resource isolation technology that can limit the resource usage of virtual machines. In particular, in an RPC-based virtualization environment, since GPU tasks executed in each virtual machine are performed in the form of multi-process, the lack of resource isolation technology causes performance degradation due to resource competition. In addition, the GPU memory competition accelerates the performance degradation as the resource demand of the virtual machines increases, and the fairness decreases because it cannot guarantee equal performance between virtual machines. This paper, in the RPC-based GPU virtualization environment, analyzes the performance degradation problem caused by resource contention when the GPU memory requirement of virtual machines exceeds the available GPU memory capacity and proposes a GPU memory management technique to solve this problem. Also, experiments show that the GPU memory management technique proposed in this paper can improve the performance of GPGPU tasks.

• Proceedings of the Korean Information Science Society Conference
• /
• 2002.10e
• /
• pp.256-258
• /
• 2002

임베디드 시스템은 임의의 시스템에 내장된 형태로 구성되고, 특정 하드웨어 구성요소를 제어하기 위하여 사용되며, 제한되고 전문화된 기능을 수행하는 장치이다. 임베디드 시스템에서 호스트간의 데이터 전송을 용이하게 하는 문서 정의 형식으로 향후 XML이 사용될 전망이다. 임베디드 시스템은 특정한 기능을 수행하기 위한 최소 용량이 요구되고 임베디드 시스템의 다양한 메모리 제한성에 부합할 수 있게 컴포넌트화도 요구된다. 본 논문에서는 임베디드 시스템에서 실행되는 응용을 위한 XML SAX2파서, mSAX를 소개한다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2006.05a
• /
• pp.1333-1336
• /
• 2006

본 논문에서는 최근에 각광받고 있는 저장장치인 플래시 메모리의 특징과 플래시 메모리의 단점인 지움 횟수 제한과 느린 지움 속도를 극복하는 지움 정책의 종류를 살펴보고 그 중에서 CAT 기법의 랜덤 쓰기에서의 지움 횟수 증가와 지움 평준화를 위한 비효율성이라는 단점을 개선한 지움 정책을 제시한다. 개선된 지움 정책은 CAT 기법에 쓰기 패턴을 기반한 가중치를 부여해 랜덤 쓰기에서의 성능 하락과 지움 평준화의 비효율성을 보완하는 것이다. 이 때 사용되는 사용자의 쓰기 패턴 파악은 유효한(valid) 데이터 블록과 유효하지 않은(invalid) 데이터 블록의 리스트를 만들어 그 시간 값의 평균을 이용한다.

• Proceedings of the IEEK Conference
• /
• 2000.09a
• /
• pp.95-97
• /
• 2000

배열 안테나에서 안테나 소자의 개수의 증가는 안테나의 이득을 증가시킬 수 있으므로 열악한 채널 환경에서도 채널이 필요로 하는 링크 마진을 얻을 수 있다. 그러나, 기존 빔 형성기에서 사용되는 배열 안테나 기법은 많은 계산량과 소모 메모리량 때문에 배열 소자의 개수에 제한이 따르게 된다. 이러한 문제를 해결하기 위하여 본 논문에서는 배열 안테나의 구조에 따른 위상차이를 보상하여 적은 계산량과 메모리를 갖는 배열 위상 차이 보상을 이용한 평행 구조 빔 형성기를 제안한다 배열 위상 차이를 보상하는 기법으로 적은 계산량과 메모리로 개수가 많은 긴 배열 안테나에서 얻을 수 있는 분해능과 안테나 이득을 얻을 수 있다. 제안된 기법의 성능을 비교하기 위해 기존의 빔 형성기법으로delay-sum 빔 형성기와 공분산 행렬의 고유치 해석을 통한 고유벡터 기법의 빔 스펙트럼과 연산량을 비교하였다. 제안된 기법으로 빔 형성을 하면, 배열 안테나의 소자의 개수가 늘어나도 기존의 방법보다 최소 30%의 연산량으로 스펙트럼 상 비슷한 성능을 얻을 수 있다.