• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.98-103
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• 1989

A new system for logic optimization at gate-level is proposed in this paper. Ths system is rule-based, i which the rules represent the local trnsformation replacing a portion of circuits with the simplified equivalent circuits. In this system, 'rule generalization' and 'local optimization' are proposed for effective pattern matching. Rule generalization is used to reduce the circuit-search for pattern matching, and local optimization, to exclude unnecessary circuit-search. In additionk, in order to reduce unnecessary trial of pattern matching, the matching order of circuit patern is included in the rule descriptions. The effectiveness of this system is shown by its application ot the circuits which are generated by a hardware compiler.

• Journal of Korea Society of Industrial Information Systems
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• v.5 no.1
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• pp.31-36
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• 2000

This paper presents a design method of deadbeat controller for DC motor driving a rotational system with gear. The deadbeat-response design developed for control system of a sampled continuous-data process does not guarantee zero intersampling ripples, but the proposed deadbeat control system that consists of the integral controller and the full-order state observer, and zero-order hold using in continuous systems, has many advantages such as an output response without the ripples and reaching the steady state without error after a given sampling period and faster settling time than the optimal control system in the same sampling period. The results of a case study through matlab simulation are shown that the efficiency of the proposed controller for DC motor driving a rotational system with gear is verified by comparing with optimal controller etc.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.94-101
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• 2002

In this paper, we propose a motion estimation algorithm for the discontinuity blocks. The algorithm uses sub-SAD value (i.e. the sum of absolute difference for a quarter of a block) to identify the discontinuity region, and produces additional motion vectors for these sub-blocks if necessary. We show with experimental results that, in comparison with some conventional motion estimation algorithms, the proposed algorithm achieves quality enhancement for the sequences with discontinuity blocks, and also shows the same computational quantity as to normal algorithms for sequences with less discontinuity.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.131-136
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• 1990

In this paper, new methods are proposed which speed up the logical redundancy identification for the gate-level logic optimization. Redundancy indentification, as well as deterministic test pattern generation, can be viewed as a finite space search problem, of which execution time depends on the size of the search space. For the purpose of efficient search, we propose dynamic head line and mandatory assignment. Dynamic head lines are changed dynamically in the process of the redundancy identification. Mandatory assignement can avoid unnecessary assignment. They can reduce the search size efficiently. Especially they can be used even though the circuit is modified in the optimization procedure, that is different from the test pattern generation methods. Some experimental results are presented indicating that the proposed methods are faster than existing methods.

• Annual Conference on Human and Language Technology
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• 2005.10a
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• pp.145-150
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• 2005

본 논문에서는 자연어 처리 연구에서 이용되는 품사 표지 부착 말뭉치의 오류 검증 방안에 대해 제안한다. 현재까지의 품사 표지 부착 말뭉치들은 정제보다는 구축에 중점을 두고 있으며, 기존의 오류 검출과 정정 방안에 관련된 연구들은 기 구축된 말뭉치를 대상으로 한 것이 아니라, 품사 표지 부착 시스템의 후 처리에 집중하고 있다. 형태소 분석기나 품사 표지 부착 시스템의 학습에 이용되는 품사 표지 부착 말뭉치가 오류 검증 단계를 거친다면 이 시스템들은 좀 더 높은 신뢰성을 가지게 될 것이다. 본 논문에서는 품사 표지부착 말뭉치 검증을 위한 어절 분할 오류, 철자 오류, 표지 부착 오류, 형식 오류, 일관성 오류의 5가지 오류 유형과 검증 방안을 제안한다. 또한 제안한 방법에 따라 세종 계획의 형태소 분석 말뭉치의 오류를 검증해 보았으며, 그 결과 말뭉치 오류 정제가 말뭉치의 신뢰도를 향상시킬 수 있음을 보인다.

• Journal of Ocean Engineering and Technology
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• v.19 no.6 s.67
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• pp.64-71
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• 2005

The welding methods have been applied to the most structural products used in the automobile, ship construction, and construction. The structure steel must have sufficient strength of structure; However, the mechanical properties of the welded part changes when it is welded. Therefore, the stability or life of the structure may be affected by the changed mechanical properties. The mechanical properties of the welded part must be examined in order to ensure the safety of structure. In this research, the SS400 steel and the STS304 steel were used to estimate the mechanical properties of the HAZ by weld thermal cycle simulation. In this study, the materials were used to examine the weld thermal cycle simulation characteristic, under two conditions: the drawing with diameter of $\Phi$10 and the residual stress removal treatment. To examine the mechanical properties by the weld thermal cycle simulation, the tensile test was carried out in room temperature. The crosshead speed was lmm/min.

• Journal of Ocean Engineering and Technology
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• v.22 no.6
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• pp.27-34
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• 2008

The temperature distribution in the weldment is not uniform because a weldment is locally heated. Thermal plastic deformation results from the local expansion and shrinkage by the heating and cooling of metal. Therefore, residual stresses and distortion occur in the weldment. In this study, we had conducted on the weld thermal cycle simulation that is supposed as the HAZ on SS400 steel and STS304 steel. The residual stresses that were obtained from the drawing and the weld thermal cycle simulation were estimated by X-ray diffraction. We also carried out ultrasonic test for the weld thermal cycle simulated specimens, and then conducted on nondestructive evaluation by the ultrasonic parameters obtained ultrasonic test. From the results, residual stresses of weld thermal cycle simulated specimens after the residual stress removal heat treatment are lower than that of the drawing.

• The Korean Journal of Financial Management
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• v.9 no.1
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• pp.135-175
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• 1992

본 논문은 주가(株價)의 변동성검증모형(變動性檢證模型)을 한국주식시장(韓國株式市場)에 적용하여 시장의 효율성을(效率性) 검증하였다. 1975년부터 1990년까지 의 17년 기간중 Shiller[81a], Mankiw-Romer-Shapiro[85], West[88b]의 모형을 이용하여 검증한 결과, 높은 수준의 과잉변동성(過剩變動性)이 발견되었다. 그러나 이러한 주가의 과잉 변동성을 시장이 비효율적이라는 증거로 간주하기는 어렵다. 왜냐하면 이들 모형의 가정 중의 하나인 할인율이 일정하다는 가정을 완화시켜 다시 검증한 결과는 오히려 과잉변동성 중에서 많은 부분이 감소하는 것으로 나타났기 때문이다. 다시말해서 주가에 과잉변동성이 존재하는 것은 시장이 비효율적이라기 보다는 기간에 따른 할인율의 변동폭이 큰 데에 원인이 있는 것으로 해석된다. 따라서 할인율(割引率)의 변동원인(變動原因)을 조사하여 주식시장의 효율성을 분석하였다. 주가의 일부는 랜덤웍의 요소에 의해 결정되고, 나머지 일부는 평균회귀(平均回歸) fads(mean reverting fads)에 의해 결정된다고 가정하여 검증한 결과, 후자에 의해 설명된 비율이 매우 높게 나타났다. 즉 한국주식시장에서의 투자자는 교란거래(攪亂去來)(noise trading)나 피드백거래(去來)(feedback trading) 등의 비합리적인 투자행동을 취하고 있으며, 이러한 비합리적인 행동에 의해 주가변동의 $60{\sim}80%$가 설명되는 것으로 보인다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.10
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• pp.73-81
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• 2000

This paper presents the design and simulation of a power and area efficient interpolation FIR filter with partitioned look up table (LUT) structure. Using the symmetry of the filters coefficients and the contents of the LUT, the area of the proposed filter is minimized. The two filters share the partitioned LUT and activate the LUT selectively to realize the low power operation. The proposed filter has been designed in a 5.0 Volts 0.6${\mu}m$ CMOS technology. Power consumption results have been obtained from Powermill simulations. Experimental results suggest that the proposed filter reduces both the power consumption by 28% and simultaneously the gate area by 5% simultaneously compared to the previously proposed filters.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.41-44
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• 2013

As appearance of high-quality service such as UDTV application, high-speed and high-capacity communication services are required. For this, communication systems increase the data processing speed and use various error correction techniques. In this paper, we implement the Viterbi decoder applied in 1000BASE-T with 4 pairs UTP cable. The minimum operating speed of the Viterbi decoer should be more than 125 MHz because 125 MHz PAM-5 signal is transmitted on each pair of cables in 1000BASE-T. To do this, we implement the decoder by using the pipeline and parallel processing and verify the operation with 125 MHz by using a logic analyzer. Finally, we will show that the decoder recovers the original data for the added random error data.