• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.1-6
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• 2010

We proposed a highly integrated 3-dimensional NOR Flash memory array by using vertical 4-bit SONOS NOR flash memory. This structure has a vertical channel, so it is possible to have a long enough channel without extra cell area. Therefore, we can avoid second-bit effect, short channel effect, and redistribution of injected charges. And the proposed array structure is based on three-dimensional integration. Thus, we can obtain a NOR flash memory having $1.5F^2$/bit cell size.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.1134-1137
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• 2008

최근 디지털 기술의 발달로 인해 디지털 캠코더, 디지털 카메라 등의 휴대용 멀티미디어 기기가 증가하고 있고, 이러한 휴대용 장치를 위한 저장 장치로 낸드 플래시가 많이 사용된다. 이러한 장치는 고화질 미디어 컨텐츠 녹화 기능을 제공하고, 녹화된 영상물은 대용량 파일 형태로 저장된다. 대용량 파일의 필요한 부분만을 편집하여 재 저장하기 위해서는 새로운 기법이 요구된다. 본 논문은 낸드 플래시 메모리 전용 파일 시스템인 YAFFS를 사용하는 멀티미디어 휴대 장치에서 멀티미디어 파일을 고속으로 편집하고 동시에 필요한 저장 공간 소모를 최소화 하는 기법을 제안한다. 동영상 파일 편집 후 저장에 있어서 현재의 낸드 플래시 파일 시스템들은 편집 내용을 빈 공간에 새로 저장하기 때문에, 대용량의 파일일수록 많은 시간과 저장 공간이 소모 된다. 본 논문에서 제안하는 기법은 동영상 편집 후 파일 간에 중복되는 데이터를 새로 저장하지 않고 공유하도록 하면서 소모되는 시간과 공간을 최소화 한다. 이를 위해 파일 간 공유 되는 데이터를 관리하는 페이지 공유 맵을 설계하고 이를 이용한 동영상 고속 편집 저장 기법을 제시한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.643-646
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• 2009

최근에 IPTV(Internet Protocol TV) 셋톱박스의 보조기억장치의 성능과 저전력을 위한 연구가 많이 수행 되고 있다. IPTV를 위한 셋톱박스의 구성품인 하드디스크는 멀티미디어 데이터를 저장하고 저장된 데이터를 재생한다. 하지만 하드디스크는 기계적인 특성으로 인하여 전력 소모 문제 및 성능 저하 문제 등이 있다. 본 논문에서는 IPTV 환경에서 하드디스크와 플래시 메모리를 혼합한 하이브리드 저장 시스템을 구성 하여 멀티미디어 데이터의 n-프레임을 플래시 메모리로 선반입 하는 새로운 방법을 제안한다. 이 방법을 통해 하드디스크의 대기시간을 줄이고 전력 사용을 최적화 할 수 있다. 실험을 통해 제안한 방법이 기존 방법과 비교하여 20.69%의 평균응답시간을 개선하고 전력소모를 28.14% 감소시킴을 확인 하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.7-14
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• 2009

Lately, NAND flash cards have been used to store massive amounts of multimedia data. However, these nand flash cells itself has a slow operation time and by that, the nand flash cards are not appropriate for high performance massive data transfer. Indeed, most flash card products have a disadvantage in that they require plenty of time to transfer massive amounts of data. Therefore, we propose a new architectural design for the hardware and software of the NAND flash cards by improving their data transfer rate. Our design is based on a multiprocessing which is different from the conventional serial processing method. We simulated our design under the VIP (Virtual IP) environment, and verified our work using FPGA test platforms. As a result, the downloading performances was approximately 160MB/s on VIP and 85.3MB/s on FPGA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.45-52
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• 2011

Flash memory is becoming widely prevalent in various area due to high performance, non-volatile features, low power, and robust durability. As price-per-bit is decreased, NAND flash based SSDs (Solid State Disk) have been attracting attention as the next generation storage device, which can replace HDDs (Hard Disk Drive) which have mechanical properties. Especially for the single package SSD, if channel number or FIFO buffer size per channel increases to improve performance, the size of a controller and I/O pin count will increase linearly with channel numbers and form factor will be affected. We propose a novel technique which can minimize form factor by optimizing the number of NAND flash channels and the size of interface FIFO buffer in the SSD. For SSD with 10 channel and double buffer, the experimental results show that buffer block size can be reduced about 73% without performance degradation and total size of a controller can be reduced about 40% because control block per channel and I/O pin count decrease according to decrease channel number.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.251-258
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• 2012

Recently, NAND Flash memory structure is evolving from SDR (Single Data Rate) to high speed DDR(Double Data Rate) to fulfill the high performance requirement of SSD and SSS. Accordingly, the proper ways of transferring data that latches valid data stably and minimizing data skew between pins by using PHY(Physical layer) circuit techniques have became new issues. Also, rapid growth of speed in NAND flash increases the operating frequency and power consumption of NAND flash controller. Internal voltage variation margin of NAND flash controller will be narrowed through the smaller geometry and lower internal operating voltage below 1.5V. Therefore, the increase of power budge deviation limits the normal operation range of internal circuit. Affection of OCV(On Chip Variation) deteriorates the voltage variation problem and thus causes internal logic errors. In this case, it is too hard to debug, because it is not functional faults. In this paper, we propose new architecture that maintains the valid timing window in cost effective way under sudden power fluctuation cases. Simulation results show that the proposed technique minimizes the data skew by 379% with reduced area by 20% compared to using PHY circuits.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.47-57
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• 2008

Recently, energy-efficient NAND Flash memory of large volume is favored as next-generation storage for sensor nodes. So far, most sensor node file systems are based on NOR flash and few file systems are applicable to large NAND flash memory. Although it is required to develop new file systems taking account of the features of NAND flash memory, it is difficult to develop them mainly due to the limit of SRAM memory on sensor nodes. Sensor nodes support SRAM of $4{\sim}10$ KBytes only. In this paper, we designed and implemented a novel file system to support data-centric applications. To do this, we added EEPROM of 1 KBytes to store persistent file description data efficiently and devised a simple wear-leveling method. This reduces the number of page updates, resulting in reduction in energy use and increase in lifetime of sensor nodes.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.78-87
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• 2013

NAND flash memory has been widely used as a storage medium in mobile devices, PCs, and workstations due to its advantages such as low power consumption, high performance, and random accessability compared to a hard disk drive. However, NAND flash cannot support in-place update so that it is mandatory to erase the entire block before overwriting the corresponding page. In order to overcome this drawback, flash storages need a software support, named Flash Translation Layer. However, as the high performance mass NAND flash memory is getting widely used, the size of mapping tables is increasing more than the limited DRAM size. In this paper, we propose an adaptive mapping information caching algorithm based on page mapping to solve this DRAM space shortage problem. Our algorithm uses a mapping information caching scheme which minimize the flash memory access frequency based on the analysis of several workloads. The experimental results show that the proposed algorithm can increase the performance by up to 70% comparing with the previous mapping information caching algorithm.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.127-135
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• 2013

In order to acquire images in low-light environments, it is usually necessary to adopt long exposure times or resort to flash lights. However, flashes often induce color distortion, cause the red-eye effect and can be disturbing to subjects. On the other hand, long-exposure shots are susceptible to subject-motion, as well as motion-blur due to camera shake when performed hand-held. A recently introduced technique to overcome the limitations of traditional low-light photography is that of multi-spectral flash. Multi-spectral flash images are a combination of UV/IR and visible spectrum information. The general idea is that of retrieving details from the UV/IR spectrum and color from the visible spectrum. However, multi-spectral flash images themselves are subject to color distortion and noise. This works presents a method to compute multi-spectral flash images so that noise can be reduced and color accuracy improved. The proposed approach is a previously seen optimization method, improved by the introduction of a weight map used to discriminate uniform regions from detail regions. The weight map is generated by applying canny edge operator and it is applied to the optimization process for discriminating the weights in uniform region and edge. Accordingly, the weight of color information is increased in the uniform region and the detail region of weight is decreased in detail region. Therefore, the proposed method can be enhancing color reproduction and removing artifacts. The performance of the proposed method has been objectively evaluated using long-exposure shots as reference.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.94-100
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• 2008

It is necessary to develop the flash memory system software FTL(Flash Translation Layer) which is used in mobile storage like Compact Flash memory. In this paper, we design the FTL using clustered hash table and two phase software caching method to translate logical address into physical address fastly. The experimental results show that the address translation performance of CFTL is 13.3% higher than that of NFTL and 8% higher than that of AFTL, and the memory usage of CFTL is 75% smaller than that of AFTL.