• Journal of IKEEE
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• v.13 no.1
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• pp.77-86
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• 2009

A wavelet Electrocardiogram(ECG) detector and its analog-to-digital converter(ADC) for low-power implantable cardiac pacemakers are presented in this paper. The proposed wavelet-based ECG detector consists of a wavelet decomposer with wavelet filter banks, a QRS complex detector of hypothesis testing with wavelet-demodulated ECG signals, and a noise detector with zero-crossing points. To achieve high-detection performance with low-power consumption, the multi-scaled product algorithm and soft-threshold algorithm are efficiently exploited. To further reduce the power dissipation, a low-power ADC, which is based on a Successive Approximation Register(SAR) architecture with an on/off-time controlled comparator and passive sample and hold, is also presented. Our algorithmic and architectural level approaches are implemented and fabricated in standard $0.35{\mu}m$ CMOS technology. The testchip shows a good detection accuracy of 99.32% and very low-power consumption of $19.02{\mu}W$ with 3-V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.83-94
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• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

• Journal of Biomedical Engineering Research
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• v.7 no.1
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• pp.59-66
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• 1986

A prototype ultrasound sector B-scanner has been developed where the front-end hardware refers to all the necessary circuits for transmitting the ultrasound pulses into the human body and receiving the reflected echo signals from it. The front-end hardware can generally be divided into three parts, i.e., a pulse generator for insonification, a receiver which is responsible for processing of low-level analog signals, and a steering controller for driving the mechanical sector probe whose functions and design concepts are described in this paper. The front-end hardware is implemented which incorporates the following features: improvement of the axial resolution using a circuit which reduces the ring-down time, flexibility of generating time-gain compensation curve, and adoption of a one-chip microcomputer for generating the rate pulses based on the sensor output waveforms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.15-22
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• 2006

In this paper, 1.8V 8-bit 500MSPS Low-power CMOS Digital-to-Analog Converter(DAC) for UWB(Ultra Wide Band) Communication Systeme is proposed. The architecture of the DAC is based on a current steering 6+2 full matrix type which has low glitch and high linearity. In order to achieve a high speed and good performance, a current cell with a high output impedance and wide swing output range is designed. Further a thermometer decoder with same delay time and low-power switching decoder for high efficiency performance are proposed. The proposed DAC was implemented with TSMC 0.18um 1-poly 6-metal N-well CMOS technology. The measured SFDR was 49dB when the output frequency was 50MHz at 500MS/s sampling frequency. The measured INL and DNL were 0.9LSB and 0.3LSB respectively. The DAC power dissipation was 20mW and the effective chip area was $0.63mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.110-116
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• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.71-79
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• 2013

This paper describes a 12.5 Gb/s low-power receiver design with equalizer adaptation. The receiver adapts to channel and chip process variation by adaptation circuit using sampler and serializer. The adaptation principle is explained. It describes technique receiving ground referenced differential signal of voltage-mode transmitter for low-power. The CTLE(Continuous Time Linear Equalizer) having 17.6 dB peaking gain to remove long tail ISI caused channel with -21 dB attenuation. The voltage margin is 210 mV and the timing margin is 0.75 UI in eye diagram. The receiver consumes 0.87 mW/Gb/s low power in 45 nm CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.3
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• pp.35-42
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• 2000

A cross-shaped microstripline-fed printed slot antenna having wide bandwidth Is presented in this paper. The proposed antenna is analyzed by using the Finite-Difference Time-Domain (FDTD) method. It was found that the bandwidth of the antenna depends highly on the length of the horizontal and vertical feedline as well as the offset position of the feedline. The maximum bandwidth of this antenna is from 1.975 GHz to 4.725 GHz, which is approximately 1.3 octave, for the VSWR $\leq$ 2. Experimental data for the return loss and the radiation pattern of the antenna are also presented. and they are in good agreement with the FDTD results.e FDTD results.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.1-6
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• 2019

An extremely small size multi-loop phase-locked loop(PLL) keeping phase noise performances has been proposed. It has been designed to have the loop filter made of small single capacitor with multiple Frequency Voltage Converters (FVCs) because the main goal is to make the size of the proposed PLL extremely small. Multiple FVCs which are connected to voltage controlled oscillator(VCO) make multiple negative feedback loops in PLL. Those multiple negative feedback loops enable the PLL with the loop filter made of an extremely small size single capacitor operate stably. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the 1.6ps jitter and $10{\mu}s$ locking time.

• 전자공학회논문지 IE
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• v.47 no.4
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• pp.1-9
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• 2010

This paper describes a ultrasonic signal processing front-end IC for distance range meter and body detector. The burst shaped ultrasonic signal is generated by a self oscillator and its frequency range is about 40[kHz]-300[kHz]. The generated ultrasonic signal transmit through piezo resonator. The another piezo device transduce from received ultrasonic signal to electrical signals. This front-end IC contained low noise amplifier, band pass filter, busrt detector and time pulse generator and so on. This IC has two type of new idea for improve function and performance, which are self frequency control (SFC) and Variable Gain Control amplifier (VGC) scheme. The dimensions and number of external parts are minimized in order to get a smaller hardware size. This device has been fabricated in a O.6[um] double poly, double metal 40[V] High Voltage CMOS process.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.265-266
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• 2012

의료용 X-ray의 발전에 따라, 영상의 Digital화가 필요하게 되었다. Digital 영상 구현을 위해 다양한 형태의 영상 검출기가 개발되었다. 진단 영상의 조건으로는 구현 시간이 빠르고 해상도가 높아야 한다. 조건에 부합하는 Flat panel 형태의 직접방식과 간접방식 검출기의 개발이 주로 이루어졌으며, X-ray 검출 효율이 높고 공간 분해능이 높은 직접 방식의 검출기에 대한 연구가 활발히 진행되고 있다. 기존 직접방식의 X-ray 검출물질로는 A-Se이 이용되었다. 하지만 A-Se의 경우 낮은 원자번호로 인해 X-ray에 대한효율이 낮으며, 제조 공정과 수율의 문제로 인해 대체 물질의 개발과 공정의 개선이 필요하다. 선행 연구를 통해 X-ray 검출물질의 전기적 특성을 파악을 통해 대체 물질로서 가능성을 알아보았다. 본 연구에서는 기존에 제작된 X-ray 검출물질의 상부전극 증착 물질과 증착법 선정에 대한 연구이다. 선행 연구를 통해 선정된 X-ray 검출물질은 HgI2이다. 상, 하부 전극 선택에 있어 HgI2의 일함수 값(4.15eV)을 고려하여 그와 비슷한 일함수 값을 가진 물질로 전기적 장벽을 제거하여야 한다. 따라서, ITO (일함수 4.45eV)와 Au (일함수 5.1eV)을 선택하였다. ITO의 증착으로 이용된 방법으로는 on-axis 형태의 magnetron plasma sputtering을 이용하였으며, Au의 증착으로 이용된 방법은 Thermal evaporation deposition을 이용하였다. plasma sputtering에 이용된 타겟은 In2O3;SnO2 (조성비:90:10wt%)를 사용하였으며, Chamber의 크기는 넓이 456 ${\phi}cm^2$ 높이 25 cm이며, 로 target과 기판과의 거리는 15cm이다. plasma발생에 필요한 가스로는 Ar과 O2를 이용하였다. 고 진공 환경 조성에 이용된 장비로는 Rotary pump와 Turbo molecular pump이다. plasma 발생 전 진공도는 $3.2{\times}10^{-5}$ Torr, 발생 후 진공도는 $5.1{\times}10^{-5}$ Torr이다. plasma 환경이 조성된 후 증착 시간은 1분 30초이다. Au는 순도 99.999%를 이용하였으며, 이용된 금은 1회 증착에 0.3 g을 이용하였다. Chamber의 넓이 1,444 ${\phi}cm^2$이며, 높이 40 cm, boat와 기판과의 거리는 25 cm이다. 고 진공 환경 조성에 이용된 장비로는 Rotary pump와 diffusion pump를 이용하였다. Au의 승화 전 진공도는 $2.4{\times}10^{-5}$ Torr 증착 시 진공도는 $4.2{\times}10^{-5}$ Torr이며, Boat에 가해준 전압, 전류는 0.97 V, 47 A이며, 증착 시간은 1분 30초이다. 광도전체 층에 각각 증착된 전극의 저항을 통해 증착상태를 판단하였다. DMM (Digital Multimeter)로 1 cm 간격으로 측정된 표면의 저항은 ITO 약 $8{\Omega}$, Au 약 $3{\Omega}$으로 전극으로서 이용이 가능한 상태이다. Au와 ITO가 증착된 HgI2 시편의 전기적 특성은 기존에 이용된 X-ray 변환물질의 성능보다 우수하였다. 하지만 Au와 ITO가 각각 증착된 시편의 전기적 특성은 큰 차이를 보이지 않았다. ITO의 경우 진공 상태에서 이용되는 Gas가 이용되며, Plasma 환경 조성 유지가 어려운 점이 있다. Au전극은 증착 환경 조성이 쉽지만, 전극 물질 이용효율이 떨어지는 단점이 있다. 본 연구를 통해 X-ray 변환물질인 HgI2의 전극물질로 Au와 ITO의 이용가능성을 알아보았다. 두 전극으로 제작된 검출기의 성능은 큰 차이 없이 우수하였고, 전기적 장벽 상태가 낮아 높은 검출 효율을 보였다. 상대적으로 Au 전극의 공정이 간단하고 수율이 높다. 하지만 Au Source의 이용 효율이 떨어지는 단점이 있다. 본 연구의 결과를 통해 공정상의 유리함과 Source의 이용효율을 고려한 분석에 대한 연구가 필요할 것으로 사료된다.