• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.14-21
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• 2011

A 10b 500MS/s $0.13{\mu}m$ CMOS ADC is proposed for 4G wireless communication systems such as a LTE-Advanced and SDR The ADC employs a calibration-free single-channel folding architecture for low power consumption and high speed conversion rate. In order to overcome the disadvantage of high folding rate, at the fine 7b ADC, a cascaded folding-interpolating technique is proposed. Further, a folding amplifier with the folded cascode output stage is also discussed in the block of folding bus, to improve the bandwidth limitation and voltage gain by parasitic capacitances. The chip has been fabricated with $0.13{\mu}m$ 1P6M CMOS technology, the effective chip area is $1.5mm^2$. The measured results of INL and DNL are within 2.95LSB and l.24LSB at 10b resolution, respectively. The SNDR is 54.8dB and SFDR is 63.4dBc when the input frequency is 9.27MHz at sampling frequency of 500MHz. The ADC consumes 150mW($300{\mu}W/MS/s$) including peripheral circuits at 500MS/s and 1.2V(1.5V) power supply.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.7
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• pp.38-45
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• 2006

The superconducting fault current limiters(SFCLs) provide the effect such as enhancement in power system reliability due to limiting the fault current within a few miliseconds. Among various SFCLs we have developed a flux-lock type SFCL and exploited a special design to effectively reduce the fault current according to properly adjustable magnetic field after the short-circuit test. This SFCL consists of two copper coils wound in parallel on the same iron core and a component using the YBCO thin film connected in series to the secondary copper coil. Meanwhile, operating characteristics can be controlled by adjusting the inductances and the winding directions of the coils. To analyze the operational characteristics, we compared closed-loop with open-loop iron core. When the applied voltage was 200[Vrms] in the additive polarity winding, the peak values of the line current the increased up to 30.71[A] in the closed-loop and 32.01[A] in the open-loop iron core, respectively. On the other hand, in the voltages generated at current limiting elements were 220.14[V] in the closed-loop and 142.73[V] in the opal-loop iron core during first-half cycle after fault instant under the same conditions. We confirmed that the open-loop iron core had lower power burden than in the closed-loop iron core. Consequently, we found that the structure of iron core enabled the flux-lock type SFCL at power system to have the flexibility.

• Polymer(Korea)
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• v.33 no.4
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• pp.377-383
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• 2009

Ionic polymer-metal composite (IPMC) actuator generates bending actuation via ion/water flux to the cathode side under an electric field. Polyelectrolytes in IPMC should possess high water-retention capability, proton conductivity, and Young's modulus. In this study. for endowing IPMCs with these properties, Nafion-alumina composite membranes containing $\alpha$- or $\gamma$-aluminas of $4{\sim}8$ wt% were prepared. Mechanical moduli of Nafion-alumina composite membranes were $7{\sim}3$ MPa higher than that of Nafion, with the slight decrease in proton conductivity. At DC 3 V. the actuation performance of the Nafion-$\alpha$-alumina (8 wt%)-IPMC was superior to that of the typical Nafion-IPMC. exhibiting 2.7 times the displacement with an enhanced blocking force. The enhanced actuation performance with the Nafion-$\alpha$-alumina composite membranes was attributed to the higher proton conductivity, the elevated ion/water flux, and the lower interfacial electric resistance of platinum electrodes and membrane, compared with those containing $\gamma$-alumina.

• Journal of the Korean Institute of Gas
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• v.25 no.3
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• pp.27-38
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• 2021

We devised the system to automatically shutdown the boiler and to fundamentally block the harmful gases, including carbon monoxide, into the indoor when the exhaust system swerves: (1) The discharge pressure of the exhaust gas decreases when the exhaust pipe is disconnected. The monitoring system of the exhaust pipe is implemented by measuring the output voltage of APS(Air Pressure Sensor) installed to control the amount of combustion air. (2) The operating software was modified so that when the system recognizes the fault condition of a flue pipe, the boiler control unit displays the fault status on the indoor regulator while shutting down the boiler. In accordance with the ventilation facility standards in the "Rules for Building Equipment Standards" by the Ministry of Land, Infrastructure and Transport, experiments were conducted to ventilate indoor air. When carbon monoxide leaked in worst-case scenario, it was possible to prevent poisoning accidents. However, since 2013, the number of indoor air exchange times has been mitigated from 0.7 to 0.5 times per hour. We observed the concentration exceeding TWA 30 ppm occasionally and thus recommend to reinforce this criterion. In conclusion, if the flue pipe fault detection and the indoor air ventilation system are introduced, carbon monoxide poisoning accidents are expected to decrease significantly. Also when the manufacturing and inspection steps, the correct installation and repair are supplemented with the user's attention in missing flue, it will be served to prevent human casualties from carbon monoxide poisoning.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.31 no.2B
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• pp.187-192
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• 2011

Nitrate nitrogen is common contaminant in groundwater aquifers, its concentration is regulated many countries below 10 mg/L as N (As per WHO standards) in drinking water. An attempt was made to get optimal results for the treatment of nitrate nitrogen in groundwater by conducting various experiments by changing the experimental conditions for ZVI bipolar packed bed electrolytic cell. From the experimental results it is evident that the nitrate nitrogen removal is more effective when the reactor conditions are maintained in acidic range but when the acidic environment changes to alkaline due to the hydroxide formed during the process of ammonia nitrogen there by increasing the pH reducing the hydrogen ions required for reduction which leads to low effectiveness of the system. In the ZVI bipolar packed bed electrolytic cell, the packing ratio of 0.5~1:1 was found to be most effective for the treatment of nitrate nitrogen because ZVI particles are isolated and individual particle act like small electrode with low packing ratio. It is seen that formation of precipitate and acceleration of clogging incrementally for packing ratio more than 2:1, decreasing the nitrate nitrogen removal rate. When the voltage is increased it is seen that kinetics and current also increases but at the same time more electric power is consumed. In this experiment, the optimum voltage was determined to be 50V. At that time, nitrate nitrogen was removed by 94.9%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.693-697
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• 2007

The SSB modem performs the modulation process which converts the digital voltage level to the audible frequency band signal and the demodulation process which converts reversely the audible frequency signal to the digital voltage level. The modulator and the demodulator are implemented with a single DSP chip. Because of the SSB specific character, the distortion occurs when the frequency is changed. This distortion has no effect on voice communication, but it has an significant effect on data communication. In other words, it is impossible to send data stream with adjacent 2 periods. Therefore, in case of using 2-tone FSK, it is needed to send at least 3 periods to transmit 1 bit. Therefore we implemented the modem using modified phase-delay shift keying to transmit 1 tone signal for high speed transmission. In the 1200[bps] mode, it generates 0, $187{\mu}s$ delay time at 1.3kHz symbol frequency, and in the 2400[bps] mode, 0, $70{\mu}s$, $130{\mu}s$, $200{\mu}s$ delay time at 1.5kHz symbol frequency. Finally, in the maximum 3600[bps] mode, it generates 0, $100{\mu}s$, $160{\mu}s$, $250{\mu}s$ delay time at 2.0kHz symbol frequency. The measured results of the implemented SSB modem shows a good transfer functional characteristic by spectrum analyzer, almost same bandwidth in pass band and 20dB higher SNR comparing the German PACTOR and American CLOVER and in the experimental transmitting test, we verified the transmitted data is received correctly in platform.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1852-1857
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• 2007

The SSB modem performs the modulation process which converts the digital voltage level to the audible frequency band signal and the demodulation process which converts reversely the audible frequency signal to the digital voltage level. The modulator and the demodulator are implemented with a single DSP chip. Because of the SSB specific character, the distortion occurs when the frequency is changed. This distortion has no effect on voice communication but it has an significant effect on data communication. In other words, it is impossible to send data stream with adjacent 2 periods. Therefore, in case of using 2-tone FSK, it is needed to send at least 3 periods to transmit 1 bit. Therefore we implemented the modem using modified phase-delay shift keying to transmit 1 tone signal for high speed transmission. In the 1200[bps] mode, it generates 0, $187{\mu}s$, delay time at 1.3kHz symbol frequency, and in the 2400[bps] mode, 0, $70{\mu}s\;130{\mu}s\;200{\mu}s$, delay time at 1.5kHz symbol frequency. Finally, in the maximum 3600[bps] mode, it generates 0, $100{\mu}s\;160{\mu}s\;250{\mu}s$ 2.0kHz symbol frequency. The measured results of the implemented SSB modem shows a good transfer functional characteristic by spectrum analyzer, almost same bandwidth in pass band and 20dB higher SNR comparing the emu FACTOR and American CLOVER and in the experimental transmitting test, we verified the transmitted data is received correctly in platform.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.4
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• pp.29-38
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• 2009

The GHP(Gas Heat Pump) is an efficient cooling;11eating system in which a compressor is driven by a gas engine and is brodening its application to the facilities such as schools and office buildings. It is difficult to control the GHP system because of slow response, big time constant and time variant system. These nonlinear loads generate harmonic currents and create distortions on the sinusoidal voltage of the power system Harmonic field measurements have shown that the harmonic contents of a waveform varies with time. A cumulative probability approach is the most commonly used method to solve time varying harmonics. This paper provides an in depth analysis on harmonics field measurement of the GHP loads, harmonic assessment by me 61000-3-2, and harmonic simulation and harmonic filter application using EDSA program for the case study system.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.1
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• pp.75-81
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• 2007

This paper dealt with the design and implementation of an expert system to monitor and diagnose the lightning arresters in GIS substations. The expert system consists of a data acquisition module(DAM) based on microprocessor and diagnostic algorithms. The DAM measures and analyzes several parameters necessary for the arrester diagnosis such as system voltages, leakage current components, and temperatures. Also, it includes an intelligent surge counter which can record the date and tin, the polarity, and the amplitude of surge currents. All the data acquired is transmitted to a remote computer by a low rate wireless network specified in IEEE 802.15.4 to avoid electromagnetic intereference under high voltage and large current environments. The decision-making for the arrester diagnosis completes with a Java Expert System Shell(JESS) which is composed of a knowledge base, an inference engine and a graphic user interface(GUI).