• Title/Summary/Keyword: 전압 발생기

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A 2-Gb/s SLVS Transmitter for MIPI D-PHY (MIPI D-PHY를 위한 2-Gb/s SLVS 송신단)

  • Baek, Seung Wuk;Jeong, Dong Gil;Park, Sang Min;Hwang, Yu Jeong;Jang, Young Chan
    • Journal of Korea Society of Industrial Information Systems
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    • v.18 no.5
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    • pp.25-32
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    • 2013
  • A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a 0.18-${\mu}m$ 1-poly 6-metal CMOS with a 1.8 V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gb/s. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

Analysis of Tunneling Current of Asymmetric Double Gate MOSFET for Ratio of Top and Bottom Gate Oxide Film Thickness (비대칭 DGMOSFET의 상하단 산화막 두께비에 따른 터널링 전류 분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.5
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    • pp.992-997
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    • 2016
  • This paper analyzes the deviation of tunneling current for the ratio of top and bottom gate oxide thickness of short channel asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current significantly increases if channel length reduces to 5 nm. This short channel effect occurs for asymmetric DGMOSFET having different top and bottom gate oxide structure. The ratio of tunneling current in off current with parameters of channel length and thickness, doping concentration, and top/bottom gate voltages is calculated in this study, and the influence of tunneling current to occur in short channel is investigated. The analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for the ratio of top and bottom gate oxide thickness in short channel asymmetric DGMOSFET, specially according to channel length, channel thickness, doping concentration, and top/bottom gate voltages.

Dependence of Drain Induced Barrier Lowering for Doping Profile of Channel in Double Gate MOSFET (이중게이트 MOSFET에서 채널내 도핑분포에 대한 드레인유기장벽감소 의존성)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.9
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    • pp.2000-2006
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    • 2011
  • In this paper, the drain induced barrier lowering(DIBL) for doping distribution in the channel has been analyzed for double gate MOSFET(DGMOSFET). The DGMOSFET is extensively been studing because of adventages to be able to reduce the short channel effects(SCEs) to occur in convensional MOSFET. DIBL is SCE known as reduction of threshold voltage due to variation of energy band by high drain voltage. This DIBL has been analyzed for structural parameter and variation of channel doping profile for DGMOSFET. For this object, The analytical model of Poisson equation has been derived from Gaussian doping distribution for DGMOSFET. To verify potential and DIBL models based on this analytical Poisson's equation, the results have been compared with those of the numerical Poisson's equation, and DIBL for DGMOSFET has been investigated using this models.

A CMOS Bandgap Reference Voltage/Current Bias Generator And Its Responses for Temperature and Radiation (CMOS Bandgap 기준 전압/전류 발생기 및 방사능 응답)

  • Lim, Gyu-Ho;Yu, Seong-Han;Heo, Jin-Seok;Kim, Kwang-Hyun;Jeon, Sung-Chae;Huh, Young;Kim, Young-Hee;Cho, Gyu-Seong
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1093-1096
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    • 2003
  • 본 논문에서는, CMOS APS Image Sensor 내에 포함되어 회로의 면적을 줄인 새롭게 제안된 CMOS Bandgap Reference Bias Generator (BGR)를 온도 및 방사능에 대한 응답을 실험하였다. 제안된 BGR 회로의 설계 목표는 V/sub DD/는 2.5V이상이고, V/sub ref/는 0.75V ± 0.5mV 마진을 가지게 하는 것이다. 제안된 BGR회로는 Level Shifter를 갖는 Differential OP-amp단과 Feedback-Loop를 가지는 Cascode Current Mirror를 사용하여 저전압에서도 동작을 가능하게 하였으며, 높은 출력저항 특성을 가지도록 하였다. 제안된 BGR회로는 하이닉스 0.18㎛ ( triple well two-poly five-metal ) CMOS 공정을 이용하여 Test Chip을 제작하였다. 온도의 변화와 Co-60 노출조건 하에서 Total ionization dose (TID) effect된 BGR회로의 V/sub ref/를 측정하여, 이를 평가하였다. 온도에 대한 반응은, 25℃ 일 때의 V/sub ref/에 대해, 각각 45 ℃에서 0.128%. 70℃에서 0.768% 변화하였다. 그리고 온도가 25℃일 때 50krad와 100krad의 방사능을 조사 하였을 경우, V/sub ref/는 각각 2.466%, 그리고 4.612% 변화하였다.

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증착 조건에 따른 ITO 전극의 X-ray 변환물질에서의 특성 평가

  • No, Seong-Jin;Sin, Jeong-Uk;Lee, Yeong-Gyu;Song, Yong-Geun;Lee, Ji-Yun;Park, Seong-Gwang;Nam, Sang-Hui
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.366-366
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    • 2012
  • 현재 사용되고 있는 투명전극재료 중에 ITO(Indium Tin Oxide)가 가장 투명하면서 전기도 잘 통하고 생산성도 좋다. 투명전극은 비저항이 $1{\times}10^{-3}{\Omega}/cm$이하, 면 저항이 $10^3{\Omega}/sq$이하로 전기전도성이 우수하고 380에서 780 nm의 가시광선 영역에서의 투과율이 80%이상이라는 두 가지 성질을 만족시키는 박막이다. 본 연구에서 X-ray Film을 제작하기 위하여 상용화된 ITO Glass 전극 기판에 X-ray가 조사되면 직접 전자 전공 쌍(electron-hole pair)을 발생시켜 전기적 신호를 발생하는 광도전체 물질(Photoconductor)인 PbO, $PbI_2$, $HgI_2$를 스크린 프린팅(Screen Printing)법을 이용하여 각각 제작하였다. 상부 전극으로 마그네틱 스퍼터링(Magnetic Sputtering) 진공 증착 장치를 사용하여 전류, 전압, 아르곤 및 산소 유입량등을 조절하면서 상부 전극을 증착하였다. 이때 타켓으로 $In_2O_3;SnO_2$ (조성비:90:10wt%)를 사용 하였고, base pressure는 $9{\times}10^{-7}torr$, deposition pressure는 $3{\times}10^5torr$를 고정하였다. 또한 전류와 전압은 각각 0.4A, 800V로 유지하고, $O_2$:0.3 ppm, Ar의 경우 4.9 ppm에서 70 ppm까지 올려 플라즈마를 활성화 시킨 후 90초 동안 ITO를 증착하였다. 본 실험에 제작된 박막으로 X-ray을 조사하여 검출기로써 특성 평가를 실시하였으며, 실험결과 X-선 투과와 전도성 등 두가지 특성이 동시에 만족 될 만한 성능을 가질 수 있음을 확인 할 수 있었다.

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A Study on characteristics of the forward type high frequency pulse power supply for lamp type ozonizer (램프형 오존발생기용 Forward type 고주파 펄스 전원장치의 특성에 관한 연구)

  • 김경식;김동희;이광식;원재선;송현직
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.14 no.2
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    • pp.89-96
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    • 2000
  • This paper describes the forward type pulse power supply which is the simple circuit configuration and easy to be managed using a power semiconductor switching device(Power-MOSFET) in the view of commercialization. The maximum value of output pulse voltage of the proposed pulse power supply system can be realized by the variation of phase angle($\phi$) of bridge rectifier circuit and also its pulse period is determined by the duty ratio of Power-MOSFET. The principle of basic operating and the operating characteristics of the forward type pulse power supply are estimated by the switching frequency, the variation of phase angle($\phi$)It is shown that theoretical and experimental results are in good agreement by comparing simulation and experimental results of proposed pulse power supply when a lamp type ozonizer can be used as a load. This proposed pulse power system shows that it can be practically used in the future as a power source system in various fields.

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A 1.8V 2-Gb/s SLVS Transmitter with 4-lane (4-lane을 가지는 1.8V 2-Gb/s SLVS 송신단)

  • Baek, Seung-Wuk;Jang, Young-Chan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.357-360
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    • 2013
  • A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a $0.18-{\mu}m$ 1-poly 6-metal CMOS with a 1.8V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gbps. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

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DC Characteristics Analysis of Various AC loads for Hybrid Distribution (하이브리드 급전을 위한 다양한 가정용 교류부하의 직류특성연구)

  • Lee, Young-Jin;Han, Dong-Ha;Choi, Jung-Muk;Jeong, Byong-Hwan;Kim, Dong-Jin;Choe, Gyu-Ha
    • The Transactions of the Korean Institute of Power Electronics
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    • v.15 no.3
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    • pp.207-217
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    • 2010
  • Recently, the use of DC power increased due to the increased use of digital load. Power factor of input current decrease and input current harmonics increase, and conversion loss which is occurred in the AC / DC converter is a problem to provide the proper DC voltage to the device equipped with an internal AC / DC converter. Hybrid system supplies the AC power and DC power to AC load (motor load and the transformer load) and DC loads (computers, TV, LED fluorescent light) at the same time it supplies the renewable energy and utility energy taken power from Utility to user for improving the efficiency and renewable energy improvements in ease of use. This paper studies DC characteristics of traditional AC load for Hybrid distributions.

A Study on Energy Efficiency of Battery Charge/Discharge System based on DC μ-Grid (DC μ-Grid 기반 배터리 충/방전 시스템의 에너지 효율에 관한 연구)

  • Yeo, Sung-Dae;Kim, Jong-Un;Lee, Kyung-Ryang;Han, Cheol-Kyu;Ryu, Tae-Hyoung;Kim, Kyeong-Hwa;Kim, Seong-Kweon
    • The Journal of the Korea institute of electronic communication sciences
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    • v.10 no.12
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    • pp.1337-1344
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    • 2015
  • Formation process through charge/discharge operation is needed in manufacturing Li-ion battery. In the process battery is discharged by a load resistor of discharger. Here, energy losses happen. Therefore, in this paper, the efficient energy operation of battery is studied in the charge/discharge system based on DC ${\mu}-Grid$. A result of computer simulation shows that if in the charge/discharge system based on DC ${\mu}-Grid$, the number of discharge batteries in comparison with three charge battery sets exceeds 133%, voltage fluctuation that occurs while the grid voltage stabilizes, which makes the system fatal. Therefore, it was demonstrated that a remarkable energy saving effect could be achieved when the number of discharge battery set is maintained to be 133% in comparison with three charge battery sets.

A study on Current-Voltage Relation for Double Gate MOSFET (DGMOSFET의 전류-전압 특성에 관한 연구)

  • Jung, Hak-Kee;Ko, Suk-Woong;Na, Young-Il;Jung, Dong-Su
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.2
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    • pp.881-883
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    • 2005
  • In case is below length 100nm of gate, various kinds problem can be happened with by threshold voltage change of device, occurrence of leakage current by tunneling because thickness of oxide by 1.5nm low scaling is done and doping concentration is increased. SiO$_2$ dielectric substance can not be used for gate insulator because is expected that tunneling current become 1A/cm$^2$ in 1.5nm thickness low. In this paper, devised double gate MOSFET(DGMOSFET) to decrease effect of leakage current by this tunneling. Therefore, could decrease effect of these leakage current in thickness 1nm low of SiO$_2$ dielectric substance. But, very big gate insulator of permittivity should be developed for develop device of nano scale.

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