• Journal of the Korean Crystal Growth and Crystal Technology
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• v.27 no.6
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• pp.275-281
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• 2017

AlN is a promising material for wide band gap and high-frequency electronics device due to its wide bandgap and high thermal conductivity. AlN has advantages as materials for power semiconductors with a larger breakdown field, and a smaller specific on-resistance at high voltage. The growth of a p-type AlN epilayer with high conductivity is important for a manufacturing an AlN-based applications. In this paper, Mg doped AlN epilayers were grown by a mixed-source HVPE. Al and Mg mixture were used as source materials for the growth of Mg-doped AlN epilayers. Mg concentration in the AlN was controlled by modulating the quantity of Mg source in the mixed-source. Surface morphology and crystalline structure of AlN epilayers with different Mg concentrations were characterized by FE-SEM and HR-XRD. XPS spectra of the Mg-doped AlN epilayers demonstrated that Mg was doped successfully into the AlN epilayer by the mixed-source HVPE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.51-60
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• 2005

The design of efficient cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. Especially, among the basic arithmetic over finite field, the rnultiplicative inversion is the most time consuming operation. In this paper, a fast inversion algerian in finite field $GF(2^m)$ with the standard basis representation is proposed. It is based on the Extended binary gcd algorithm (EBGA). The proposed algorithm executes about $18.8\%\;or\;45.9\%$ less iterations than EBGA or Montgomery inverse algorithm (MIA), respectively. In practical applications where the dimension of the field is large or may vary, systolic array sDucture becomes area-complexity and time-complexity costly or even impractical in previous algorithms. It is not suitable for low-weight and low-power systems, i.e., smartcard, the mobile phone. In this paper, we propose a new hardware architecture to apply an area-efficient and a synchronized inverter on low-complexity systems. It requires the number of addition and reduction operation less than previous architectures for computing the inverses in $GF(2^m)$ furthermore, the proposed inversion is applied over either prime or binary extension fields, more specially $GF(2^m)$ and GF(P) .

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.74-85
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• 2015

PCI Express is a well-known and widely used de-facto system bus standard for connecting among a processor and IO devices. PCI Express is originated from old PCI standard, and its most of applications are limited to be used within a PC or server system. But, because of its fast speed, low power consumption, and good protocol efficiency, it is considered as one of a good candidate for an alternate system interconnect for many years. In this paper, we present design, implementation and early evaluation of an alternate system interconnect by utilizing PCI Express. The developed alternate system interconnect using PCI Express (named PCIeLINK) utilizes non-transparent bridging (NTB) technic which generally used in fail-over system in PCI and PCI Express. By using NTB technic, PCI Express device can be extended to outside of a system without electrical and logical problems arising during system boot and enumeration. To build up an alternate system interconnect, we designed and implemented a network interface card having multiple PCI Express ${\times}4$ connections (theoretically 20 Gbps) and tested, The early test results revealed that an ${\times}4$ port in the card showed 8.6 Gbps peak performance for bulk transmission and 5.1 Gbps peak for normal TCP/IP transfer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.29-38
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• 2009

In this paper, a high performance pipelined computing design of parallel multiplier-temporal buffer-parallel accumulator is present for the convolution-based non-cascaded architecture aiming at the real time Discrete Wavelet Transform(DWT) processing. The convolved multiplication of DWT would be reduced upto 1/4 by utilizing the filter coefficients symmetry and the up/down sampling; and it could be dealt with 3-5 times faster computation by LUT-based DA multiplication of multiple filter coefficients parallelized for product terms with an image data. Further, the reutilization of computed product terms could be achieved by storing in the temporal buffer, which yields the saving of computation as well as dynamic power by 50%. The convolved product terms of image data and filter coefficients are realigned and stored in the temporal buffer for the accumulated addition. Then, the buffer management of parallel aligned storage is carried out for the high speed sequential retrieval of parallel accumulations. The convolved computation is pipelined with parallel multiplier-temporal buffer-parallel accumulation in which the parallelization of temporal buffer and accumulator is optimize, with respect to the performance of parallel DA multiplier, to improve the pipelining performance. The proposed architecture is back-end designed with 0.18um library, which verifies the 30fps throughput of SVGA(800$\times$600) images at 90MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.40-49
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• 2011

Integrating massive components and low-power policies have been actively investigated for system-on-chip designs. But in recent years, finding the optimal interconnection structure among heterogeneous components has emerged as a critical system design issue. Therefore, various simulation tools to model interconnection designs are being developed and performance evaluation of simulation is reflected in the real design. But most of the simulation environments employ traffic generation based on the mathematical probability functions, and such traffic generation cannot fully cover for various situations that may be occurred in the real system. Therefore, the demand for traffic pattern generation based on real applications is increasing. However, there have been few simulators that adopt application-specific traffic generators. This paper proposes a novel traffic generation method in simulating various interconnection structures for multi-processor system-on-chip design. The proposed traffic generation method can generate traffic patterns that can reflect the actual characteristics of the application and evaluate the performance of an interconnection structure under more realistic circumstance than traffic patterns using mathematical probability functions. By comparing the differences between the proposed method and the one based on mathematical probability functions, this paper shows advantages of the proposed traffic generation method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.71-81
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• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

• Journal of the Korean GEO-environmental Society
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• v.21 no.9
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• pp.25-32
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• 2020

The underground utilities installed under the ground is an important civil engineering structure, such as water supply and sewerage pipes, underground power lines, various communication lines, and city gas pipes. Such underground utilities can be exposed to risk due to external factors such as concentrated rainfall and vehicle load, and it is important to select and construct an appropriate backfill material. Currently, a method mainly used is to fill the soil around the underground utilities and compact it. But it is difficult to compact the lower part of the buried pipe and the compaction efficiency decreases, reducing the stability of the underground utilities and causing various damages. In addition, there are disadvantages such as a decrease in ground strength due to disturbance of the ground, a complicated construction process, and construction costs increase because the construction period becomes longer, and civil complaints due to traffic restrictions. One way to solve this problem is to use a liquid filler. The liquid filler has advantages such as self-leveling ability, self-compaction, fluidity, artificial strength control, and low strength that can be re-excavated for maintenance. In this study, uniaxial compression strength test and fluidity test were performed to characterize the mixed soil using marine clay, stabilizer, and in-situ soil as backfill material. A freezing-thawing test was performed to understand the strength characteristics of the liquid filler by freezing, and in order to examine the effect of the filling materials on the corrosion of the underground pipe, an electrical resistivity test and a pH test were performed.

• Journal of Bio-Environment Control
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• v.18 no.1
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• pp.23-28
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• 2009

This study was conducted to evaluate the effect of optimized environment conditions with growth stage in photoautotrophic micropropagation on the growth of potato (Solanum tuberosum L. cv. Dejima) plantlets and energy efficiency. Optimum environment conditions at each stage were decided in our previous study. For the evaluation of optimized environment control, potato plantlets were cultured under four different conditions: photoautotrophic optimum conditions of photosynthetic photon flux density (PPFD) and $CO_2$ levels with growth stage (POG), photoautotrophic constant condition with average PPFD and $CO_2$ levels (PCA), photoauototrophic constant condition with maximum PPFD and $CO_2$ levels (PCM), and photomixotrophic conventional condition with 3% sucrose (PMC) as control. As a result, environment control with growth stage (POG) significantly promoted all the growth characteristics such as the number of nodes and unfolded leaves, shoot height, shoot diameter, and fresh and dry weights of potato grown in vitro. In addition, based on dry weight consumed electricity and $CO_2$ were the lowest in POG suggesting the highest energy efficiency among the treatments. After transferring potato plantlets to greenhouse, the plantlets under POG showed vigorous growth, which was pretty similar with those under PMC. The accumulations of dry matter in POG were 4.7 times in vitro and 3.8 times in greenhouse as much as those in the conventional control (PCM). Thus, we concluded that in vitro environment control with growth stage induced vigorous growth of potato plantlets both in vitro and in greenhouse with less energy consumption.