• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.82-90
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• 2014

In this paper, a couple of 4-channel differential transimpedance amplifier arrays are realized in a standard 0.18um CMOS technology for the applications of linear LADAR(laser detection and ranging) systems. Each array targets 1.25-Gb/s operations, where the current-mode chip consists of current-mirror input stage, a single-to-differential amplifier, and an output buffer. The input stage exploits the local feedback current-mirror configuration for low input resistance and low noise characteristics. Measurements demonstrate that each channel achieves $69-dB{\Omega}$ transimpedance gain, 2.2-GHz bandwidth, 21.5-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -20.5-dBm), and the 4-channel total power dissipation of 147.6-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations. Meanwhile, the voltage-mode chip consists of inverter input stage for low noise characteristics, a single-to-differential amplifier, and an output buffer. Test chips reveal that each channel achieves $73-dB{\Omega}$ transimpedance gain, 1.1-GHz bandwidth, 13.2-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -22.8-dBm), and the 4-channel total power dissipation of 138.4-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.6-13
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• 2009

For X-band phased array systems, a power amplifier, a 6-bit phase shifter, a 6-bit digital attenuator, and a SPDT transmit/receive (T/R) switch are fabricated and measured. All circuits are demonstrated by using CMOS 0.18 um technology. The power amplifier has 2-stage differential and cascade structures. It provides 1-dB gain-compressed output power ($P_{1dB}$) of 20 dBm and power-added-efficiency (PAE) of 19 % at 8-11 GHz frequencies. The 6-bit phase shifter utilizes embedded switched filter structure which consists of nMOS transistors as a switch and meandered microstrip lines for desired inductances. It has $360^{\circ}$ phase-control range and $5.6^{\circ}$ phase resolution. At 8-11 GHz frequencies, it has RMS phase and amplitude errors are below $5^{\circ}$ and 0.8 dB, and insertion loss of $-15.7\;{\pm}\;1,1\;dB$. The 6-bit digital attenuator is comprised of embedded switched Pi-and T-type attenuators resistive networks and nMOS switches and employes compensation circuits for low insertion phase variation. It has max. attenuation of 31.5 dB and 0.5 dB amplitude resolution. Its RMS amplitude and phase errors are below 0.4 dB and $2^{\circ}$ at 8-11 GHz frequencies, and insertion loss is $-10.5\;{\pm}\;0.8\;dB$. The SPDT T/R switch has series and shunt transistor pairs on transmit and receive path, and only one inductance to reduce chip area. It shows insertion loss of -1.5 dB, return loss below -15 dB, and isolation about -30 dB. The fabricated chip areas are $1.28\;mm^2$, $1.9mm^2$, $0.34\;mm^2$, $0.02mm^2$, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.47-54
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• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.6
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• pp.715-720
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• 2016

This paper proposes a PWM (Pulse Width Modulation) voltage mode DC-DC step-up converter for portable devices. The converter, which is operated with a 1 MHz switching frequency, is capable of reducing the mounting area of passive devices, such as inductor and capacitor, and is suitable for compact mobile products. This step-up converter consists of a power stage and a control block. The circuit elements of the power stage are an inductor, output capacitor, MOS transistors Meanwhile, control block consist of OPAMP (operational amplifier), BGR (band gap reference), soft-start, hysteresis comparator, and non-overlap driver and some protection circuits (OVP, TSD, UVLO). The hysteresis comparator and non-overlapping drivers reduce the output ripple and the effects of noise to improve safety. The proposed step-up converter was designed and verified in Magnachip/Hynix 0.18um 1-poly, 6-metal CMOS process technology. The output voltage was 5 V with a 3.3 V input voltage, output current of 100 mA, output ripple less than 1% of the output voltage, and a switching frequency of 1 MHz. These designed DC-DC step-up converters could be applied to the Personal Digital Assistants(PDA), cellular Phones, Laptop Computer, etc.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.227-247
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• 2015

An X-band $8{\times}16$ dual-polarized active phased array antenna system has been implemented based on the substrate integrated waveguide(SIW) technology having low propagation loss, complete EM shielding, and high power handling characteristics. Compared with the microstrip case, 1 dB less is the measured insertion loss(0.65 dB) of the 16-way SIW power distribution network and doubled(3 dB improved) is the measured radiation efficiency(73 %) of the SIW sub-array($1{\times}16$) antenna element. These significant improvements of the power division loss and the radiation efficiency using the SIW, save more than 30 % of the total power consumption, in the active phased array antenna systems, through substantial reduction of the maximum output power(P1 dB) of the high power amplifiers. Using the X-band $8{\times}16$ dual-polarized active phased array antenna system fabricated by the SIW technology, the main radiation beam has been steered by 0, 5, 9, and 18 degrees in the accuracy of 2 degree maximum deviation by simply generating the theoretical control vectors. Performing thermal cycle and vacuum tests, we have found that the SIW array antenna system be eligible for the space environment qualification. We expect that the high efficiency SIW array antenna system be very effective for high performance radar systems, massive MIMO for 5G mobile systems, and various millimeter-wave systems(60 GHz WPAN, 77 GHz automotive radars, high speed digital transmission systems).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.14-21
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• 2011

A 10b 500MS/s $0.13{\mu}m$ CMOS ADC is proposed for 4G wireless communication systems such as a LTE-Advanced and SDR The ADC employs a calibration-free single-channel folding architecture for low power consumption and high speed conversion rate. In order to overcome the disadvantage of high folding rate, at the fine 7b ADC, a cascaded folding-interpolating technique is proposed. Further, a folding amplifier with the folded cascode output stage is also discussed in the block of folding bus, to improve the bandwidth limitation and voltage gain by parasitic capacitances. The chip has been fabricated with $0.13{\mu}m$ 1P6M CMOS technology, the effective chip area is $1.5mm^2$. The measured results of INL and DNL are within 2.95LSB and l.24LSB at 10b resolution, respectively. The SNDR is 54.8dB and SFDR is 63.4dBc when the input frequency is 9.27MHz at sampling frequency of 500MHz. The ADC consumes 150mW($300{\mu}W/MS/s$) including peripheral circuits at 500MS/s and 1.2V(1.5V) power supply.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.39-47
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• 1998

A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.1
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• pp.76-84
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• 2012

In this paper, two kinds of E-plane microstrip-to-waveguide transitions are optimally designed and fabricated for combining output power from multiple small-power amplifiers in a WR-28 waveguide because conventional K connectors cause unnecessary insertion loss and adaptor loss. The transition design is based on target specifications such as a center frequency of 35 GHz, bandwidth of ${\pm}500MHz$, 0.1 dB insertion loss and 20 dB return loss. Performance variation caused by mechanical tolerance and assembly deviation is fully evaluated by three dimensional electromagnetic simulation. The fabricated back-to-back transitions with 16 mm and 26.57 mm interstage microstrip lines show insertion loss per transition of ~0.1 dB at 35 GHz and average 0.2 dB over full Ka band. Also the back-to-back transition shows return loss greater than 15 dB, which implies that the transition itself has return loss better than 20 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.183-190
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• 2007

This paper presents the design of 860 MHz band transmitter for improving power amplifier's linearity using Cartesian feedback method. For eliminating the effects of gain, phase mis-match, and DC offset, we estimate the property variations using ADS software. The implemented Cartesian feedback transmitter exhibits IMD3 of -54 dBc at an output power of 43 dBm and this result shows that the linearity is improved for 22.4 dB, compared with the test of the power amplifier without Cartesian feedback system. Thus, we verify that the proposed Cartesian feedback transmitter can be applied to narrow-band transmitter systems.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.62-62
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• 2000

비접촉식 온도센서는 물체에서 방출하는 적외선 등의 복사신호를 열에너지로 전환하고 이를 다시 전기신호로 2차 에너지 변환하여 온도를 감지하는 센서로 인체 검지를 응용한 다양한 상품 및 교통, 방재, 빌딩 시스템 등의 분야에 널리 응용되고 있다. 비접촉식 적외선 센서는 열에너지를 전기에너지로 변환하는 방법에 따라 양자형과 열형으로 구분되며, 이중 양자형은 광전도나 광기전력 효과 등을 이용하여 감도 및 응답성이 우수하다는 장점을 지니고 있지만, 소자부를 80K 이하 온도로 유지시키는 냉각을 필요로 하므로 대형 제작이 불가피하고 그 용도가 제한적이다. 열형은 냉각이 필요 없고 소형으로 제작가능한 장점을 지니고 있어 써모 파일이나 초전체를 이용한 번용 센서가 보급되고 있다. 그러나 써모파일의 경우 출력되는 전기 신호가 미약하여 감도 및 응답성을 향상하기 위해 구조가 복잡하고, 특히 모터초퍼나 저항을 전압으로 변환시키는 전력기 등이 필요로 하는 단점을 지니고 있다. 따라서 이러한 문제점을 보완하기 위해 열전재료 박막을 이용한 적외선 센서를 개발하려는 노력이 진행중에 있다. 열전박막을 이용한 적외선 센서는 열전재료의 Seebeck 현상을 이용하여 열에너지에서 전기에너지의 변환이 자가발전으로 이루어져 offset과 외부 바이어스를 필요로 하지 않는다. 또한 작은 온도 변화에도 그 감도와 응답성이 높고, 출력신호가 커서 증폭기 등이 불필요한 장점을 지니고 있다. 특히 초전형 센서가 상온에서도 기판에 대한 열 확산을 제어해야 하는 문제점을 갖는 반면, 열전박막형 적외선 센서는 고온에서도 안정된 출력 신호를 얻을 수 있어 그 활용 온도 범위가 크게 확대될 것으로 기대된다. 본 실험에서는 우수한 열전특성을 갖는 (Bi1-xSbx)2Te3 박막을 얻기 위해 열팽창계수가 작고 알칼리 원소가 0.3% 이하로 포함되어 있는 corning glass(# 7059)를 기판으로 사용하였다. 또한 최적의 열전특성을 나타내는 조성을 실험적으로 구하기 위해 (Bi0.2Sbx)2Te3 조성의 합금 타？ 위에 Bi2Te3 및 Sb2Te3 chip을 올려놓고 그 면적을 변화시켜 다양한 조성의 열전박막을 증착하였다. 열전박막의 증착시 산화와 오염에 의한 열전특성 변화를 최소화하기 위해 초기진공도를 1$\times$10-6 Torr로 하였으며, Ar 가스를 흘려주어 2$\times$102 Torr 의 증착진공도를 유지하였다. 열전박막을 증착하기 전에 기판을 10분간 200W의 출력으로 RF 처리하였으며, 30$0^{\circ}C$에서 33 /sec의 속도로 (Bi1-xSbx)2Te3 박막을 증착하였다. 이와 같이 제조된 (Bi1-xSbx)2Te3 박막의 미세구조를 SEM으로 관찰하고 EDS로 조성을 분석하였으며, XRD를 이용하여 결정성을 관찰하였다. 또한 (Bi1-xSbx)2Te3 박막의 Seebeeck 계수 및 전기비저항을 측정하고 증착된 박막조성, 결정상, 미세구조와 열전특성간의 상관관계를 고찰하였다.