• Maritime Security
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• v.1 no.1
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• pp.215-240
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• 2020

In 2017, the U.S. DARPA coined 'mosaic warfare' as a new way of warfighting. According to the Timothy Grayson, director of DARPA's Strategic Technologies Office, mosaic warfare is a "system of system" approach to warfghting designed around compatible "tiles" of capabilities, rather than uniquely shaped "puzzle pieces" that must be fitted into a specific slot in a battle plan in order for it to work. Prior to cover mosaic warfare theory and recent development, it deals analyze its background and several premises for better understanding. The U.S. DoD officials might acknowledge the current its forces vulnerability to the China's A2/AD assets. Furthermore, the U.S. seeks to complete military superiority even in other nation's territorial domains including sea and air. Given its rapid combat restoration capability and less manpower casualty, the U.S. would be able to ready to endure war of attrition that requires massive resources. The core concept of mosaic warfare is a "decision centric warfare". To embody this idea, it create adaptability for U.S. forces and complexity or uncertainty for the enemy through the rapid composition and recomposition of a more disag g reg ated U.S. military force using human command and machine control. This allows providing more options to friendly forces and collapse adversary's OODA loop eventually. Adaptable kill web, composable force packages, A.I., and context-centric C3 architecture are crucial elements to implement and carry out mosaic warfare. Recently, CSBA showed an compelling assessment of mosaic warfare simulation. In this wargame, there was a significant differences between traditional and mosaic teams. Mosaic team was able to mount more simultaneous actions, creating additional complexity to adversaries and overwhelming their decision-making with less friendly force's human casualty. It increase the speed of the U.S. force's decision-making, enabling commanders to better employ tempo. Consequently, this article finds out and suggests implications for Korea armed forces. First of all, it needs to examine and develop 'mosaic warfare' in terms of our security circumstance. In response to future warfare, reviewing overall force structure and architecture is required which is able to compose force element regardless domain. In regards to insufficient defense resources and budget, "choice" and "concentration" are also essential. It needs to have eyes on the neighboring countries' development of future war concept carefully.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2337-2342
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• 2010

There is a vast field of application for RFID(Radio Frequency IDentification) technology. In the case of hospitals, RFID can be used for organizing patient data. Generally, patient data has been handled with medical cards. In order to look up data about a patient, the medical card would have to be found first, within a lot of other medical cards, by hand or with a computer. This is a very inconvenient system. Also, if the card is searched by the name of the patient, fatal medical accidents may occur in cases of mix-ups. If remote RFID Tag monitoring systems are applied in this case, the patient data would be accessible in the hospital. This article will discuss the grafting of RFID systems and wireless data communicating technology. The EM4095 chip, which uses 125KHz carrier waves was used in this study. And a Bluetooth module was added for wireless data communication. The ATMEGA128 microcomputer was used to control the RFID system and wireless module. A LCD monitor was connected to the extension port for nurses to view patient data, and also, the same information was displayed on PC monitors for doctors to see. The circuit was designed to consume minimal amounts of electricity for portability, and to transmit Tag ID's in environments with a lot of noise. The article is concluded with a diagram of the whole system, and performance of each data transmitting section has been analyzed.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.274-276
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• 2002

Ad Hoc망은 전형적인 무선 네트워킹과는 다른 새로운 무선 네트워킹 파라다임으로써 기존 유선 망의 하부 구조에 의존하지 않고 이동 호스트들로만 구성된 네트워크이다. Ad Hoc망에서 통신을 하기 위해서는 출발지 노드에서 목적지 노드까지 데이터 전송을 위한 라우팅에 관한 문제이다. Ad Hoc망에서는 모든 단말기의 위치변화가 가능하기 때문에 경로설정에 어려움이 따른다. 노드간에 정보를 보내고자 할 때 노드가 인접한 상태가 아니면 정보를 직접 보낼 수 없고 여러 중간 노드들을 거쳐서 정보를 보내는 다중-홉 라우팅 방식을 사용해야 한다. 따라서 중간 노드들은 패킷 라우터의 역할을 해야하는데 무선 통신자체가 좁은 대역폭과 한정된 채널을 가지고 전송 범위가 제한되는 문제가 있다. 또한 노드자체의 이동성과 전력 소모 등으로 인한 이탈은 망 위상을 수시로 변화시키므로 노드간에 정보를 전송하는데 가장 좋은 경로는 수시로 변경될 수 있으므로 많은 어려움이 따르게 된다. 본 논문에서는 이러한 문제의 해결방안으로 경로유지 과정에서 Ad Hoc망 내의 노드들은 이동성의 특성으로 인해 현재 사용되는 경로 보다 더 짧고 효율적인 경로가 발생하고 중간 노드가 이동 될 때 새로운 경로로 갱신하여 솔기없는 최적의 경로를 유지할 수 있는 방법을 제안한다. 제안 방법은 ZRP의 IERP에서 감청모드를 통하여 사용중인 경로보다 최적의 경로를 감지하여 새로운 경로로 갱신하는 방법과 중간 노드가 이동하여 경로가 깨진 경우 부분적으로 경로를 복구하는 방법을 제시하여 항상 최적화된 경로를 유지함으로써 Ad Hoc망의 위상변화에 대한 적응성을 높일 수 있도록 한다.기반으로 하는 교육용 애플리케이션 개발의 용이성의 증대를 기대할 수 있으며, 모델의 재사용성을 보장할 수 있다. 제안한다.수행하였다. 분석에서는 제품의 효율성뿐만 아니라 보안성을 중요하게 생각하였으며, 앞으로 보안 관련 소프트웨어 개발에 사용될 수 있는 도구들이 가이드 라인에 대한 정보를 제공한다.용할 수 있는지 세부 설계를 제시한다.다.으로서 hemicellulose구조가 polyuronic acid의 형태인 것으로 사료된다. 추출획분의 구성단당은 여러 곡물연구의 보고와 유사하게 glucose, arabinose, xylose 함량이 대체로 높게 나타났다. 점미가 수가용성분에서 goucose대비 용출함량이 고르게 나타나는 경향을 보였고 흑미는 알칼리가용분에서 glucose가 상당량(0.68%) 포함되고 있음을 보여주었고 arabinose(0.68%), xylose(0.05%)도 다른 종류에 비해서 다량 함유한 것으로 나타났다. 흑미는 총식이섬유 함량이 높고 pectic substances, hemicellulose, uronic acid 함량이 높아서 콜레스테롤 저하 등의 효과가 기대되며 고섬유식품으로서 조리 특성 연구가 필요한 것으로 사료된다.리하였다. 얻어진 소견(所見)은 다음과 같았다. 1. 모년령(母年齡), 임신회수(姙娠回數), 임신기간(姙娠其間), 출산시체중등(出産時體重等)의 제요인(諸要因)은 주산기사망(周産基死亡)에 대(對)하여 통계적(統計的)으로 유의(有意)한 영향을 미치고 있어 $25{\sim}29$세(歲)의 연령군에서, 2번째 임신과 2번째의 출산에서 그리고 만삭의 임신 기간에, 출산시체중(出産時體重

• Journal of Mushroom
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• v.12 no.4
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• pp.270-274
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• 2014

In previous studies, we selected the green LED(light emitting diodes) for suitable wavelength of the light by higher commercial yields and lower ratio of the abnormal fruit body in Lentinula edodes. In this study, we aimed to select efficient irradiation intensity of the green LED. Stronger irradiation intensity of the green LED resulted in more polyphenol content of fruit body. And Polyphenol content of fluorescent lamp was similar to that of the green LED $20umol{\cdot}m^{-2}{\cdot}s^{-1}$.. Ergosterol content of the green LED $5umol{\cdot}m^{-2}{\cdot}s^{-1}$ was showed higher 2.1 times than that of the fluorescent lamp. In four level of irradiation intensity, 5, 10, 15, $20umol{\cdot}m^{-2}{\cdot}s^{-1}$ there was no big difference in characteristics of the fruit body. However the yield of fruit body in the green LED $5umol{\cdot}m^{-2}{\cdot}s^{-1}$ is higher than the others. In addition, The amount of electricity used of the green LED $5umol{\cdot}m^{-2}{\cdot}s^{-1}$ was reduced 15.9% than that of the fluorescent lamp. In conclusion, we selected $5umol{\cdot}m^{-2}{\cdot}s^{-1}$ for suitable irradiation intensity in Lentinula edodes with sawdust substrate cultivation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.71-81
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• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

• Journal of Digital Convergence
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• v.18 no.3
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• pp.163-169
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• 2020

A smart key has been used in a variety of embedded environments and there also have been attacks from a remote place by amplifying signals at a location of a user. Existing studies on defence techniques suggest multiple sensors and hash functions to improve authentication speed; these, however, increase the electricity usage and the probability of type 1 error. For these reasons, I suggest an embedded security controller based on client authentication and user movement information improving the authentication method between a controller and a host device. I applied encryption algorithm to the suggested model for communication using an Arduino board, GPS, and Bluetooth and performed authentication through path analysis utilizing user movement information for the authentication. I found that the change in usability was nonsignificant when performing actions using the suggested model by evaluating the time to encode and decode. The embedded security controller in the model can be applied to the system of a remote controller for a two-wheeled vehicle or a mobile and stationary host device; in the process of studying, I found that encryption and decryption could take less then 100ms. The later study may deal with protocols to speed up the data communication including encryption and decryption and the path data management.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.