• Journal of Advanced Navigation Technology
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• v.22 no.4
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• pp.319-324
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• 2018

In this paper, a high power amplifier using RF power solid-state semiconductor is implemented to overcome a problem of plasma generator which has the low efficiency, short life span, the difficult maintenance and the high-operation cost. This power amplifier consists of a radial combiner of low-loss and high power operation and the sixteen 300 W power amplifiers to obtain 3 kW output power for high power operation implemented in semiconductors at industrial scientific medical (ISM) band of 2.45 GHz. In addition, this amplifier overcomes the problem of heat generation due to high power by applying a water-cooled structure to the individual amplifiers. This power amplifier, which is made up of a small system, achieves 50% efficiency at the desired output.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.1
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• pp.13-20
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• 2015

Existing LDMOS power amplifier that used class-AB and doherty system shows 55% of efficiency in 60MHz narrow band. Because RRH has been applied to power amplifier at base station. It is required that over 100MHz expanded band and more than 60% high efficiency power amplifier. In this paper we designed class-J power amplifier using LDMOS FET which has over 60% high efficiency characteristic in 200MHz. The output matching circuit of designed class-J power amplifier has been optimized to contain pure reactance at second harmonic load and has low quality factor Q. As a measurement result of the amplifier, when we input continuous wave signal, we checked 62~70% of power added efficiency(PAE) in 2.06~2.2GHz including WCDMA frequency as a 10W class-J power amplifier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.6 s.121
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• pp.584-590
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• 2007

In this paper, the efficiency of power amplifier has been maximized by the application of EER structure, and the linearity has been improved by using PBG structure. This paper has proposed a design of power amplifier in class-F to get the PAE, and to control dynamic power using envelope detector. PBG structure gets high-linearity by removing harmonics arisen from the mismatching of matching circuit. The PAE and the 3rd order IMD have been improved 34.64%, 6.65 dB compared with those of conventional Doherty amplifier, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.4
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• pp.479-486
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• 1999

In this paper the system performance degradation resulting from nonlinear transmitter power amplifier which is essential to increase the efficiency is analyzed in a forward link CDMA system. The power amplifier is modeled by power series model which includes only odd-order terms. The effects of power amplifier's nonlinearity such as intersymbol interference, phase distortion on the RF system performance were visualized by examining the distorted time domain waveforms, signal vector constellation. And through the investigation of the power spectrum density of the transmitted signal, spectral regrowth or sideband regrowth which is result from amplitude distortion can be seen. All these characteristics result in BER performance degradation due to other user interferences and intersymbol interference. The analysis technique described here applies not only to power amplifier but also to any other nonlinear components such as mixers and switches. Also the effects of adjacent channel interference and supurious emission can be analysed between different systems.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.540-547
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• 2004

In this paper, a current - mode class D(CMCD) power amplifier over 70 % power added efficiency at 900 ㎒ is designed and implemented. Based on push-pull class B structure, main power loss due to charge and discharge of output capacitance in switching mode power amplifier is minimized by applying a parallel harmonic control circuit. Experimental CMCD amplifier with 73 % power added efficiency at 3.2 W and 72 % power added efficiency at 5 W are achieved respectively. In addition a characteristic of switching mode power amplifier whose output power is proportional to magnitude of U power is verified.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.1
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• pp.110-114
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• 2008

In this paper, high efficient class F power amplifier with dual band has been realized. Dual band power amplifier have used modify stub matching for single FET, center frequency 2.14GHz and 5.2GHz respectively. Dual band amplifier is 32.65dBm output power, gain 11dB and PAE 36% at the 2.14GHz, 7dB gain at the 5.2GHz. Design of a dual band class F power amplifier using harmonic control circuit. The measured are 9.9dB gain, 30dBm output power and PAE 55% at the 2.14GHz, 11.7dB gain at the 5.2GHz. This paper is being used the load-pull method and it maximizes output power and it is using the only one transistor in the paper. As a result, this research will obtain a dual band high PAE power amplifier.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.815-817
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• 2012

본 논문에서는 차량 충돌 예방 레이더 시스템-온-칩용 77GHz 고주파 전단부(RF front-end)를 제안한다. 이러한 고주파 전단부는 77GHz의 동작주파수를 가진 저 잡음 증폭기와 고주파 전력 증폭기로 구성된다. 이러한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정 ($f_T/f_{MAX}=120/140GHz$)으로 설계되어 있다. 저잡음 증폭기의 경우 전압이득이 36dB로 최근 발표된 연구결과 중 가장 우수한 수치를 보였다. 전력 증폭기는 포화전력과 출력 $P_{1dB}$이 18dBm과 15dBm으로 기존 연구결과 중 가장 우수한 결과를 각각 보였다.

• Journal of Satellite, Information and Communications
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• v.12 no.4
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• pp.115-119
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• 2017

Intermodulation distortion degrades the S/N(signal-to-noise) of the original signal and also affects the adjacent channels. Intermodulation distortion is mainly caused by the nonlinear characteristics of the power amplifier. If the power amplifier with nonlinear characteristics has a memory effect, the intermodulation distortions occurred in the power amplifier are generated in various and complex forms. The predistorter is used as a way to improve intermodulation distortions. In order to efficiently utilize the performance of the predistorter, the memory effect of the power amplifier must be reduced. In this paper, we describe the design method of bias circuit to reduce the memory effect in power amplifiers. To reduce the memory effect, the bias circuit must have a high impedance for the signal and a low impedance for the envelope(modulating signal) and the second harmonic component of the signal. To verify the performance of the bias circuit designed considering the memory effect, a power amplifier operating at 170 ~ 220MHz was designed and implemented. The designed bias circuit has a large impedance in the operating frequency band and low impedance in the envelope signal and the second harmonic of the signal. As a result of the performance measurement, it was found that the asymmetric intermodulation distortion component is improved by 3.7dB.

• Journal of Advanced Navigation Technology
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• v.21 no.6
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• pp.626-632
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• 2017

This paper describes a high power amplifier combining eight low power amplifiers using a radial power combiner with low insertion loss. The radial power combiner is a non-resonant type combiner with 8 input ports and is implemented by microstrip transmission line. The combiner characteristics designed at operating frequency of 1.045 GHz have an insertion loss of 0.7 dB and a return loss of more than 12 dB. Also, the low power amplifier used was designed with AFT27S010NT1 transistor and designed to satisfy the same gain, phase and constant output characteristic at operating frequency. The high power amplifier, which combiners the radial power combiner and the drive amplifier of 8 W output by driving low power amplifiers obtained the output characteristic of 33 W at operating frequency of 1.045 GHz. Also, the change of the output characteristic of the amplifier using the radial combiner was graceful degradation when the low power amplifier failed one by one.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.12
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• pp.1-6
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• 2008

In this paper, bias control circuit structure have been employed to improve the power added efficiency of the CMOS class-E power amplifier on low input power level. The gate and drain bias voltage has been controlled with the envelope of the input RF signal. The proposed CMOS class-E power amplifier using bias controlled circuit has been improved the PAE on low output power level. The operating frequency is 2.14GHz and the output power is 22dBm to 25dBm. In addition to, it has been evident that the designed the structure has showed more than a 80% increase in PAE for flatness over all input power level, respectively.