• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.53-61
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• 2008

Consider a typical wireless sensor network in which stem nodes form the backbone network of mesh topology while each stem node together with leaf nodes in its vicinity forms a subnetwork of star topology. In such a wireless sensor network, we must heed the following when we design a MAC scheme supporting the packet delivery from a leaf node to a stem node. First, leaf nodes are usually battery-powered and it is difficult to change or recharge their batteries. Secondly, a wireless sensor network is often deployed to collect and update data periodically. Late delivery of a data segment by a sensor node causes the sink node to defer data processing and the data segment itself to be obsolete. Thirdly, extensive signaling is extremely limited and complex computation is hardly supported. Taking account of these facts, a MAC scheme must be able to save energy and support timeliness in packet delivery while being simple and robust as well. In this paper, we propose a version of ALOHA as a MAC scheme for a wireless sensor network. While conserving the simplicity and robustness of the original version of ALOHA, the proposed version of ALOHA possesses a distinctive feature that a sensor node decides between stop and continuation prior to each delivery attempt for a packet. Such a decision needs a stopping rule and we suggest a Bayes stopping rule. Note that a Bayes stopping rule minimizes the Bayes risk which reflects the energy, timeliness and throughput losses. Also, a Bayes stopping rule is practical since a sensor node makes a decision only using its own history of delivery attempt results and the prior information about the failure in delivery attempt. Numerical examples confirm that the proposed version of ALOHA employing a Bayes stopping rule is a useful MAC scheme in the severe environment of wireless sensor network.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.16-27
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• 2017

IEEE 802.15.6 standard, a Wireless Body Area Network, aims to transfer not only medical data but also non-medical data, such as physical activity, streaming, multimedia game, living information, and entertainment. Services which transfer those data have very various data rates, intervals and frequencies of continuous access to a medium. Therefore, an efficient anti-collision operations and medium assigning operation have to be carried out when multiple nodes with different data rates are accessing shared medium. IEEE 802.15.6 standard for CSMA/CA medium access control method distributes access to the shared medium, transmits a control packet to avoid collision and checks status of the channel. This method is energy inefficient and causes overhead. These disadvantages conflict with the low power, low cost calculation requirement of wireless body area network, shall minimize such overhead for efficient wireless body area network operations. Therefore, in this paper, we propose a medium access scheduling scheme, which adjusts the time interval for accessing to the shared transmission medium according to the amount of data for generating respective sensor node, and a priority control algorithm, which temporarily adjusts the priority of the sensor node that causes transmission concession due to the data priority until next successful transmission to ensure fairness.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.

• Journal of IKEEE
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• v.19 no.4
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• pp.491-499
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• 2015

Silicon Carbide(SiC) has large advantage in high temperature and high voltage applications because of its high thermal conductivity and large band gap energy. When using SiC to design power semiconductor devices, edge termination techniques have to be adjusted for its maximum breakdown voltage characteristics. Many edge termination techniques have been proposed, and the most appropriate technique for SiC device is Junction Termination Extension(JTE). In this paper, the change of breakdown voltage efficiency ratio according to the change of doping concentration and passivation oxide charge of each JTE techniques is demonstrated. As a result, the maximum breakdown voltage ratio of Single Zone JTE(SZ-JTE), Double Zone JTE(DZ-JTE), Multiple Floating Zone JTE(MFZ-JTE), and Space Modulated JTE(SM-JTE) is 98.24%, 99.02%, 98.98%, 99.22% each. MFZ-JTE has the smallest and SZ-JTE has the largest sensitivity of breakdown voltage ratios according to the change of JTE doping concentration. Additionally the degradation of breakdown voltage due to the passivation oxide charge is analyzed, and the sensitivity is largest in SZ-JTE and smallest in MFZ-JTE, too. In this paper, DZ-JTE and SM-JTE is the best efficiency JTE techniques than MFZ-JTE which needs large doping concentration in short JTE width.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.35-41
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• 2020

Fast Fourier transform (FFT) processors have been widely used in various application such as communications, image, and biomedical signal processing. Especially, high-performance and low-power FFT processing is indispensable in OFDM-based communication systems. This paper presents a novel radix-26 FFT algorithm with low computational complexity and high hardware efficiency. Applying a 7-dimensional index mapping, the twiddle factor is decomposed and then radix-26 FFT algorithm is derived. The proposed algorithm has a simple twiddle factor sequence and a small number of complex multiplications, which can reduce the memory size for storing the twiddle factor. When the coefficient of twiddle factor is small, complex constant multipliers can be used efficiently instead of complex multipliers. Complex constant multipliers can be designed more efficiently using canonic signed digit (CSD) and common subexpression elimination (CSE) algorithm. An efficient complex constant multiplier design method for the twiddle factor multiplication used in the proposed radix-26 algorithm is proposed applying CSD and CSE algorithm. To evaluate performance of the previous and the proposed methods, 256-point single-path delay feedback (SDF) FFT is designed and synthesized into FPGA. The proposed algorithm uses about 10% less hardware than the previous algorithm.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.425-431
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• 2020

Recent advancements in industries and technologies have resulted in an increase in the volume of transportation, management, and distribution of logistics. Radio-frequency identification (RFID) technologies have been developed to efficiently manage such a large amount of logistics information. The use of RFID for management is being applied not only to the logistics industry, but also to the power transmission and energy management field. However, due to the limitation of program development capacity, the RFID device is limited in development, and this limitation is vulnerable to security because the existing strong encryption method cannot be used. For this reason, we designed a chaotic system for security with simple operations that are easy to apply to such a restricted environment of RFID. The designed system is a two-dimensional tent map chaotic system. In order to solve the problem of a biased distribution of signals according to the parameters of the chaotic dynamical system, the system has a cryptographic parameter(𝜇₁), a distribution parameter(𝜇₂), and a parameter(𝜃), which is the constant point, ID value, that can be used as a key value. The designed RFID authentication system is similar to random numbers, and it has the characteristics of chaotic signals that can be reproduced with initial values. It can also solve the problem of a biased distribution of parameters, so it is deemed to be more effective than the existing encryption method using the chaotic system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.436-442
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• 2020

ESS(energy storage system) has recently become an important power source in various areas due to increased renewable energy resources. The more ESS is used, the less the effective capacity of the ESS. Therefore, it is important to manage the remaining useful lifetime(RUL). RUL can be checked regularly by inspectors, but it is common to be monitored and estimated by an automated monitoring system. The accurate state estimation is important to ESS operator for economical and efficient operation. RUL estimation model usually requires complex mathematical calculations consisting of cycle aging and calendar aging that are caused by the operation frequency and over time, respectively. A lightweight RUL estimation model is required to be embedded in low-performance processors that are installed on ESS. In this paper, a lightweight ESS RUL estimation model is proposed to operate on low-performance micro-processors. The simulation results show less than 1% errors compared to the original RUL model case. In addition, a performance analysis is conducted based on ATmega 328. The results show 76.8 to 78.3 % of computational time reduction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.279-279
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• 2007

비휘발성 메모리 Fe-RAM은 빠른 정보처리 속도와 전원공급이 차단되었을 때도 계속 정보를 유지할 수 있는 비휘발성 특징과 더불어 저전압, 저전력 구동의 장점이 있어서, 차세대 메모리로 많은 주목을 받고 있다. FeRAM에 사용되는 강유전체는 주로 Pb(Zr,Ti)$O_3$가 적용되었는데, 최근에는 비납계 강유전체의 연구도 활발히 이루어지고 있다. 이러한 비납계 강유전체 중에서 가장 특성이 우수한 물질은 $(Bi,La)_4Ti_3O_{12}$ (BLT) 이다. 그런데 BLT는 결정 방향에 따른 강한 이방성의 강유전 특성을 나타내기 때문에 BLT 박막을 이용하여 Fe-RAM 소자 등을 제작하기 위해서는 결정의 방향성을 세심하게 제어하는 것이 매우 중요하다. 지금까지 연구된 BLT 박막의 방향성 조절결과를 보면, BLT 박막을 스핀 코팅 법 (spin coating method)으로 증착하고, 핵생성 열처리 단계를 조절하여 무작위 방향성을 갖는 박막을 제조하는 방법이 일반적이었다. 그런데 이러한 스핀 코팅법에서의 핵생성 단계의 제어는 공정 조건 확보가 너무 어려운 단점이 있다. 이러한 어려움을 극복할 수 있는 대안은 스퍼터링 증착법(sputtering deposition method), PLD (pulsed laser deposition)법 등과 같은 PVD (physical vapor deposition) 법의 증착방법을 적용하는 것이다. PVD 법으로 증착하는 경우에는 이미 박막 내에 무수한 결정핵이 존재하기 때문에 핵생성 단계가 필요가 없게 된다. PVD 증착법의 적용을 위해서는 타겟의 제조 및 평가 실험이 선행되어야 한다. 그런데 벌크 BLT 재료의 소결공정 조건과 전기적 특성에 관한 연구 결과는 거의 발표가 되지 않고 있다. 본 실험에서는 $Bi_2O_3,\;TiO_2,\;La_2O_3,\;Nb_2O_5\;and\;Al_2O_3$ 분말들을 이용하여 최적의 조성을 구하기 위하여 $Nb^{+5}$ 와 $Al^{+3}$을 $Ti^{+4}$ 자리에 소량 치환시켜 제조하였다. 혼합된 분말을 하소 후 pellet 형태로 성형하여 소결을 실시하였다. 시편을 1mm 두께로 연마하고, 양면에 silver 전극을 인쇄하여 전기적 특성을 측정하였다. 측정결과 $Ti^{+4}$ 자리에 $Nb^{+5}$를 치환하여 제조한 시편에서 $2P_r{\sim}31\;{\mu}c/cm^2$정도의 매우 우수한 특성을 얻었다.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1397-1398
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• 2007

본 연구는 $SF_6$와 Dry-air(건조공기), $N_2$, $CO_2$ 가스가 혼합된 절연매체의 절연 특성과 부분방전 특성 연구를 기초실험용 쳄버와 70kV급 GIS mock up을 이용하여 교류전압을 인가하여 실험이 수행되었다. 전자의 경우, Sphere gap 및 Needle/Plate 전극시스템을 이용하여 순수 $SF_6$가스와 Dry-air, $N_2$, $CO_2$ 가스들의 절연내력을 비교하고, 챔버의 압력을 5기압으로 유지한 상태에서 Dry-air, $N_2$, $CO_2$와 $SF_6$가스의 혼합비를 변화시키면서 절연내력이 측정되었다. 후자의 경우, 기초실험에서 도출된 $SF_6$가스와 Dry-air, $N_2$, $CO_2$의 최적의 혼합비율을 선택한 후, 방전 개시전압과 부분방전 양상을 순수 $SF_6$가스의 결과와 비교분석하기 위한 실험을 수행하였다. 이를 위하여 GIS 사고의 주요원인이 되는 결함들, 즉 Protrusion, Floating, Free moving particle 들을 인위적으로 모의하여 Mock up 내부에 설치하고 내부 압력을 5기압으로 유지한 상태에서 수행되었다. 전자의 경우, $0.5{\sim}5$ 기압 범위 내에서 Dry-air, $N_2$, $CO_2$ 압력을 변화시켰을 때 절연내력은 전극시스템에 무관하게 순수 $SF_6$가스의 결과치의 Dir-air $47{\sim}51%$, $N_2\;48{\sim}61%$, $CO_2\;47{\sim}60%$ 정도이다. 또한 챔버 압력이 5기압인 상태에서 Dry-air, $N_2$, $CO_2$가 80% 혼합된 절연매체는 순수 $SF_6$가스 절연내력의 80%이상의 절연내력을 가지고 있다. 후자의 경우, 인가전압을 고정 시켰을 때, 부분방전 패턴과 방전크기는, 순수 $SF_6$가스와 Dry-air 가 80% 혼합된 절연매체는 동일한 패턴과 방전크기를 나타내고 있다. 이러한 결과를 근거로, 가스 압력이 5기압에서 운전되는 전력기기의 절연매체로서 혼합가스를 사용할 경우, $SF_6$가스와 Dry-air, $CO_2$, $N_2$ 가스들의 혼합비는 2:8정도가 적절한 것으로 제안한다.