• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.4
• /
• pp.9-9
• /
• 2001

반도체 소자가 소형화 되면서 소자의 신뢰성을 유지하고 전력 소모를 줄이기 위해 기가-비트 DRAM의 동작 전압은 1.5V 이하로 줄어들 것으로 기대된다. 따라서 기가-비트 DRAM을 구현하기 위해 저전압 회로 설계 기술이 요구된다. 이 연구에서는 지금까지 발표된 저전압 DRAM 회로 설계 기술에 대한 조사결과를 기술하였고, 기가-비트 DRAM을 위해 4가지 종류의 저전압 회로 설계 기술을 새로이 제안하였다. 이 4가지 저전압 회로 설계 기술은 subthreshold 누설 전류를 줄이는 계층적 negative-voltage word-line 구동기, two-phase VBB(Back-Bias Voltage) 발생기, two-phase VPP(Boosted Voltage) 발생기와 밴드갭 기준전압 발생기에 대한 것인데, 이에 대한 테스트 칩의 측정 결과와 SPICE 시뮬레이션 결과를 제시하였다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.8B
• /
• pp.1477-1486
• /
• 2000

This paper proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit design.. The proposed algorithm decreases the power consumption by partitioning a given circuit utilizing a kernel, and reduces the area overhead by minimizing duplicated gates in the partitioned subcircuits. Experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating circuits consuming 43.6% less power with 30.7% less area on the average, when compared to the previous algorithm based on precomputation circuit structure.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2017.11a
• /
• pp.1254-1257
• /
• 2017

LoRa는 저전력 및 장거리 작동을 위해 설계된 새로운 ISM 대역 무선 기술이며, LoRaWAN은 LoRa에서 정의된 광역 네트워크 프로토콜이다. 본 논문에서는 실제 환경에서 LoRaWAN 기술의 통신 성능을 검증하는 것을 목표로 한다. 이를 위해, 캠퍼스 내에 LoRaWAN 실험을 위한 실제 테스트 베드를 구축했다. 사용자들이 사용하는 실제 환경을 만들기 위해 통신 게이트웨이를 실내에 설치하였고, 캠퍼스의 실내외 다수 위치에서 데이터를 P2P 방식으로 게이트웨이에게 전송한다. 실험에서는 대역폭, 코딩 속도, 확산 계수 및 전송 전력을 변화시켰으며, 성능 검증을 위해 신호대잡음비와 패킷 전송률을 측정하여 결과를 분석한다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.7
• /
• pp.1379-1385
• /
• 2009

We propose a low-power and high-speed client receiver for a mobile display digital interface (MDDI) newly in this paper. The low-power receiver is designed such that bias currents, sink and source currents, are insensitive to variations of power supply, process, temperature, and common-mode input voltage (VCM) and is able to operate at a rate of 450Mbps or above under the conditions of a power supply range of 3.0 to 3.6Vand a temperature range of -40 to 85$^{\circ}$C. And it is confirmed by a simulation result that the current dissipation is less than 500${\mu}$A. A test chip is manufactured with the Magna chip 0.35${\mu}$m CMOS process. When a test was done, the data receiver and data recovery circuits are functioning normally.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.1
• /
• pp.81-90
• /
• 2004

The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique . based on m-block partition is introduced in this paper. By the m-block partition algorithm, the dependencies among groups of state variables are minimized and switching activity is further reduced by assigning the codes of the states in the same group considering the state transition probability among the states. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on state variables. It is inherently contradictory problem to optimize the testability and power consumption simultaneously, however our new state assignment technique is able to achieve high fault coverage with less number of scan nfp flops by reducing the number of feedback cycles while the power consumption is kept low upon the low switching activities among state variables. Experiment shows drastic improvement in testabilities and power dissipation for benchmark circuits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.892-895
• /
• 2011

Power consumption during testing System-On-Chip (SOC) are becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.12
• /
• pp.2366-2373
• /
• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.10 no.1
• /
• pp.73-80
• /
• 2015

The valve device is installed in hazardous areas, such as a chemical plant explosion has been sealed with fire protection device to prevent the risk of explosion. In this paper, due to the explosion-proof devices using external power the device can not be used in infrared sensors and Zigbee sensor valve device by measuring the open degree of valve opening and closing of the danger zone to check whether. Valve opening and closing operation log screen time, we propose a low-power operation monitoring system administrators to manage and control the plant. Develop power control relay board apply an improved algorithm to apply the asynchronous LPL power management. The plant monitoring system and explosion-proof valve opening and closing the valve system with the intelligent device designed and implemented and tested it.

• Proceedings of the Korean Information Science Society Conference
• /
• 2002.10e
• /
• pp.118-120
• /
• 2002

블루투스는 저 전력과 휴대성이 높은 특징을 갖는 단거리 무선 통신 기술이며 다양한 응용 범위를 지니고 있어 차세대 통신기술로 각광받고 있다. 이에 따라 다양한 블루투스서비스들의 요구가 증대되고 있고 이들의 개발에 필요한 프로토콜 스택의 중요성 또한 커지고 있다. 본 논문에서는 오픈소스 프로토콜 스택인 OpenBT를 블루투스 모듈과 호스트 사이에서 중요한 역할을 하는 HCI를 중심으로 분석하였으며 이를 기반으로 한 응용 프로그램의 구현 및 테스트에 관하여 논하였다

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.6
• /
• pp.28-36
• /
• 2008

This paper describes a low-power CMOS analog front-end block for UHF band RFID tag chips. It satisfies ISO/IEC 18000-6C and includes a memory block for test. For reducing power consumption, it operates with an internally generated power supply of 1V. An ASK demodulator using a current-mode schmitt trigger is proposed and designed. The proposed demodulator can more exactly demodulate than conventional demodulator with low current consumption. It is designed using a $0.18{\mu}m$ CMOS technology. Measurement results show that it can operate properly with an input as low as $0.25V_{peak}$ and consumes $2.63{\mu}A$. The chip size is $0.12mm^2$.