• 대한방사선방어학회:학술대회논문집
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• 2011.11a
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• pp.262-263
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• 2011

• Journal of Korea Multimedia Society
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• v.6 no.1
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• pp.161-166
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• 2003

This paper presents a high gain LNA for a bluetooth application using 0.25$\mu\textrm{m}$ CMOS technology. The conventional one stage LNA has a low power gain. The presented one stage LNA using a cascode inverter LNA with a voltage reference and without a choke inductor has an improved Power gain. Simulation results of the 2.4GHz designed LNA shows a high power gain of 21dB, a noise figure of 2.2dB, and the power consumption of 255mW at 2.5V power supply.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.5
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• pp.587-592
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• 2015

According to increase in the use of the LED, the demand for low power consumption LED display design of the controller block has increased. In this paper, the low power LED controller block was designed through the power source supply that leads adiabatic operation from constant current source circuit operated by digital signal control. The proposed circuit was implemented using a 0.35um CMOS process. and it demonstrated linear operation of the circuit. From the simulation result, the proposed circuit was evaluated with about 82% power consumption reduction effect in comparison with conventional LED controller block. This research is expected to be helpful for the low power operation and the solution for heat problem of LED display.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.441-444
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• 2007

본 논문에서는 객체기반 IP 스토리지를 이용하여 모바일 기기에서 멀티미디어 콘텐츠 재생에 적합한 저전력 객체기반 모바일 스토리지 시스템 구조를 제안한다. 멀티미디어 콘텐츠의 재생 성능을 높이기 위해 모바일 단말 측 OSD 계층에 버퍼 캐시(buffer cache)와 선반입(prefetch) 기능을 추가한다. 그리고 모바일 단말의 WLAN 전력제어를 통하여 WLAN이 가능한 한 오랜 시간 동안 Sleep 상태 또는 Power Off 상태에 있을 수 있도록 하여 전력의 소비를 줄인다. 본 연구에서는 캐시 및 선반입 기능을 위해 버퍼 캐시관리자(buffer cache manager)와 선반입 관리자(prefetch manager)를 설계하였고, WLAN 전력관리 기능을 위해 WLAN 관리자(WLAN manager)를 설계하였다.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2649-2651
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• 2004

본 논문에서는 다중객체 인식 시스템과 같은 저용량 데이터전송의 저전력 무선센서네트워크 분야에 적용 가능한 새로운 펄스 방식의 저용량 UWB 통신 시스템을 제안하고 이를 설계 및 구현한다. 특히, 펄스방식의 저전력 UWB 시스템을 구현하기 위해서 전형적인 통신시스템의 수신기 구조인 RF단의 믹서, 상관기와 A/D 변환기를 없애고 최대한 단순화된 구조의 무선 비동기방식의 초광대역 송수신기를 설계한다. 설계된 WAU(Wireless Asynchronous Ultra-Wide band)시스템은 홈내 또는 강의실과 같은 곳에서 1:N HD(Half Duplex) 방식으로 저전력 무선 CANVAS 전송이 가능토록 실제 구현되었다. 구현된 WAU 시스템은 P-to-P(Peer-to-Peer) LOS(Line of Sight) 채널상태의 전송거리 10 m 에서 안정적으로 최대 115kbps 급의 전송속도가 지원 가능함을 측정하였다.

• Journal of the Korean Institute of Intelligent Systems
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• v.19 no.2
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• pp.180-184
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• 2009

The memory is very sensitive to the soft error because the integration of the memory increases under low power environment. Error correcting codes (ECCs) are commonly used to protect against the soft errors. This paper proposes a new genetic ECC design method which reduces power consumption. Power is minimized using the degrees of freedom in selecting the parity check matrix of the ECCs. Therefore, the genetic algorithm which has the novel genetic operators tailored for this formulation is employed to solve the non-linear power optimization problem. Experiments are performed with Hamming code and Hsiao code to illustrate the performance of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.134-139
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• 2006

In this paper we present the Low-Power Bus Driven Floorplan(BDF) in which the bus power consumption is minimized by using a new cost function. The previously reported BDF has used the cost function which minimizes only the chid and the bus area. However, such a cost function may not consider the bus power consumption determined by the topology of a bus in case of the segmented bus design. In this paper, we formulate a new cost function which. reflects the communication frequency and the real distance between blocks in a bus to model the bus power consumption. For the Low-Power BDF with the new cost function, the experimental results show the bus power consumption cost is reduced by 11.43% on the average.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.93-96
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• 2001

본 논문에서는 고속 저전력 곱셈기에 적합한 CPA(Carry Propagation Adder)부분의 ENMODL (Enhanced NORA MODL) 설계방식을 제안한다. ENMODL 설계방식은 반복성이 많은 CLA(Carry-Look-ahead Adder) 가산기와 같은 회로에서 많은 면적을 줄일 수 있고 동작 속도를 빠르게 할 수 있다. 따라서 본 논문에서는 저전력 고속 곱셈기에 적합한 CPA 부분을 ENMODL CLA 가산기로 설계했고 현대 0.6$\mu\textrm{m}$ 2-poly 3-metal 공정파라미터를 이용하여 HSPICE로 시뮬레이션 하여 회로의 성능을 확인하였다. 또한, CADENCE tool을 이용하여 16비트 곱셈기에 적합한 ENMODL CLA를 레이아웃 하여 칩 제작 중에 있다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.5
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• pp.193-197
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• 2017

In this paper, we present a low-power delta-sigma based digital frequency synthesizer with high frequency resolution for bio sensor networks. Biomedical radio-frequency (RF) transceivers require miniaturized forms with a long battery life and low power consumption. For the technology scaling, digital circuits have become preferable compared to analog circuits because of the aggressive cost, size, flexibility, and repeatability. Therefore, the digital circuits based on standard-cell library are used to reduce a power consumption. Additionally, a delta-sigma is used for making fractional frequency tuning range. From the simulation, we confirmed that proposed scheme has good performance in accordance with power and frequency resolution.

• Journal of IKEEE
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• v.12 no.4
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• pp.211-216
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• 2008

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.