• Journal of Satellite, Information and Communications
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• v.8 no.3
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• pp.10-14
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• 2013

In this paper, when applying current-mode circuit design technique showing constant power dissipation none the less operation frequency, to the low power design of dynamic voltage frequency scaling, we introduce the low power current-mode circuit design technique applying MOSFET in sub-threshold region, in order to solve the problem that has large power dissipation especially on the condition of low operating frequency. BSIM 3, was used as a MOSFET model in circuit simulation. From the simulation result, the power dissipation of the current memory circuit with sub-threshold MOSFET showed $18.98{\mu}W$, which means the consumption reduction effect of 98%, compared with $900{\mu}W$ in that with strong inversion. It is confirmed that the proposed circuit design technique will be available in DVFS using a current-mode circuit design.

• Fire Science and Engineering
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• v.26 no.1
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• pp.74-79
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• 2012

This study is described for development of the stand-alone smoke and heat detector (SASHD) according to the revised in 2011 type approval and performance inspection code for detector. The main improvement of the revised regulation is source. CMOS microcontroller with nano watt technology is use for development of the workable SASHD over 10 years. The low-power SASHD is developed by using the power-saving sleep mode of microcontroller, by making the low-power source voltage checker, heat detector and smoke detector. The stand-alone detector is developed by smoke and heat detector type for reduce false fire alarm. User can choose type of work between the heat detection mode and smoke & heat detection mode. The SASHD can communicate with each them using RS-485 communication supported from microcontroller. So, this study can develop the SASHD that is able to alarm more wide area when fire occurs and reduce a flash fire alarm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.66-72
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• 2009

In this paper, an efficient frequency offset synchronization structure for OFDM(Orthogonal Frequency Division Multiplexing) is proposed. Conventional CORDIC(Coordinate Rotation Digital Computer) algorithm for frequency offset synchronization utilizes two CORDIC hardware i.e., one is vector mode for phase estimation, the other is rotation mode for compensation. But proposed structure utilizes one CORDIC hardware and divider. Through simulation, it is shown that hardware implementation complexity is reduced compared with conventional structures. The Verilog-HDL coding and front-end chip implementation results for the proposed structure show 22.1% gate count reduction comparison with those of the conventional structure.

• Journal of IKEEE
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• v.11 no.2
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• pp.83-88
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• 2007

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The 8${\times}$8 multiplier is designed with proposed MCML full adders and conventional full adders. The designed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. This circuit is designed with Samsung 0.35${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4A
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• pp.365-372
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• 2007

In IEEE 802.11b wireless network, stations synchronize themselves to the beacons periodically sent by the access point(AP) when they are running in low power mode. In case of missing beacon due to noise or traffic from neighboring wireless network stations must be awake until they get the next beacon, which causes energy consumption in stations. In this paper, we propose a scheme searching next beacon consuming little energy. The problems of missing beacon in low power mode of IEEE 802.11b wireless interface are described and a new method to reduce energy consumption is proposed. The proposed method is simulated with the network simulator, ns2, and compared with the low power mode of the IEEE 802.11b. The result measured in terms of station's wakeup time shows some enhancement in energy consumption when some errors occur in receiving frames.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1A
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• pp.65-71
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• 2006

In IEEE 802.11b wireless network, the access point(AP) sends beacons periodically to manage stations when they are running in low power mode. Stations contend for the transmission medium after they receive a beacon and continuously check its state until it becomes available. Thus the energy consumption of each station increases as the load of wireless network. In this paper, we propose a method to reduce energy consumption controlling virtual bitmap in wireless network with multiple stations. The problems of low power mode in IEEE 802.11b wireless interface are described and a new method to reduce energy consumption is proposed. The proposed method is simulated with the network simulator, ns2, and compared with the low power mode of the IEEE 802.11b. The result measured in terms of station's wakeup time shows some enhancement in energy consumption when multiple stations are communicating through the AP in wireless network.

• Proceedings of the Korea Contents Association Conference
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• 2012.05a
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• pp.27-28
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• 2012

최근 테블릿 PC 및 스마트폰과 같은 휴대용 전자제품의 사용량이 증가되고 있다. 이러한 휴대용 기기들은 배터리로 동작하기 때문에 실제 사용시간이 제한된다는 특징을 가진다. 이렇게 배터리로 동작하는 임베디드 시스템은 애플리케이션을 보다 오랜 시간 동안 동작할 수 있도록 저전력 기법이 적용된 운영체제를 필요로 한다. 본 논문에서는 스마트폰과 같은 휴대용 기기들에서 사용할 수 있는 실시간 운영체제인 CNU_RTOS에 S3C2440 칩셋에서 제공하는 CPU 상태 모드를 이용한 저전력 기법을 구현하여 전력 감소율을 측정하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2B
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• pp.215-224
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• 2010

A container security device (CSD) monitors intrusions through the cargo door; it is a reduced function device that uses IEEE 802.15.4 with a beacon mode. However, in the beacon mode, the CSD consumes too much battery power in periodical idle listening and sensing trials. Moreover, the CSD cannot send the message to the CSD reader actively, and it makes big latency problem. Therefore, we propose a low-power CSD to reduce the unnecessary power consumption. The proposed CSD follows the requirements of the U.S. Department of Homeland Security, and reduces battery consumption through a power-efficient hardware design, a night-watch mechanism for low-power operation and low-power sensing to reduce unnecessary monitoring. And the CSD sends alert message to the CSD reader. Simulation results show that our CSD reduces battery consumption by over 70% through the night-watch mechanism and by approximately 80% through the low-power sensing. And the CSD can send the alert message to the remote CSD reader by over 94%.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.68-71
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• 2004

본 연구는 저전압 AC 전류원으로부터 밧데리 충전을 위한 에너지 변환회로를 제안한다. 전체 시스템의 소형화 및 고효율화를 추구하기 위해서, 풀브리지 MOSFET 정류기와 부스트 컨버터로 회로를 구성하였다. 제안된 컨버터 시스템의 동작원리 및 동작모드를 해석하고, 시뮬레이션을 통해 해석결과를 검증하였다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.39-45
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• 2009

OFDM is used for achieving a high-speed data transmission in mobile wireless communication systems. Conventionally, fast Fourier transform that is the main signal processing of OFDM is implemented using digital signal processing. The DSP FFT LSI requires large power consumption. Current-mode FFT LSI with analog signal processing is one of the best solutions for high speed and low power consumption. However, for the operation of current-mode FFT LSI that has the structure of parallel-input and parallel-output, current-mode serial-to-parallel and parallel-to-serial converter are indispensable. We propose a novel current-mode SPC and PSC and full chip simulation results agree with experimental data. The proposed current-mode SPC and PSC promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.