• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.8
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• pp.610-618
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• 2017

This paper presents a 868/915 MHz CMOS RF transceiver for the ZigBee application. Using a switchless matching network, the off chip switch is removed to achieve the low cost RF transceiver, and by the elimination of the switch's insertion loss we can achieve the benefits for the RF receiver's noise figure and transmitter's power efficiency at the given output power. The receiver is composed of low-noise amplifier, mixer, and baseband analog(BBA) circuit. The transmitter is composed of BBA, mixer, and driver amplifier. And, the integer N type frequency synthesizer is designed. The proposed ZigBee RF full transceiver is implemented on the $0.18{\mu}m$ CMOS technology. Measurement results show that the maximum gain and the noise figure of the receiver are 97.6 dB and 6.8 dB, respectively. The receiver consumes 32 mA in the receiver mode and the transmitter 33 mA in the transmission mode.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2004.11a
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• pp.295-298
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• 2004

본 논문에서는 휴대용 영상장비인 비디오 레코더에 사용되는 직렬구조 리튬이온 배터리의 보호회로를 제안하였다. 제안된 보호회의에서는 정적 전류소모가 큰 전지 상태 검출기를 공유하였고 배터리의 상태에 따른 저 전력모드 변환을 가능하게 하여 보호회로의 효율성을 극대화하였다. 제안된 회의는 0.35um 표준 CMOS 공정을 사용하여 검증하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.565-570
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• 2012

This paper has proposed a multi-channel low pass filter (LPF) for LTE-Advanced systems. The proposed LPF is an active-RC 5th chebyshev topology with three cut-off frequencies of 5 MHz, 10 MHz, and 40 MHz. A 3-bit tuning circuit has been adopted to prevent variations of each cut-off frequency from process, voltage, and temperature (PVT). To achieve a high cut-off frequency of 40 MHz, an operational amplifier used in the proposed filter has employed a PMOS cross-connection load with a negative impedance. A proposed filter has been implemented in a 0.13-${\mu}m$ CMOS technology and consumes 20.2 mW with a 1.2 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.93-101
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• 2007

Small area and low power implementation are important requirements for various multimedia processing hardware, especially for mobile environment. This paper presents a hardware architecture of H.264/AVC Intra Prediction module aiming on small area and low power. A single arithmetic unit was shared and processed sequentially for all mode decisions and computations to predict an image frame. As a result, we could get smaller area and smaller memory size compared to other existing implementations. The proposed architecture was verified using the Altera Excalibur device, and the implemented hardware has been described in Verilog-HDL and synthesized on Samsung STD130 0.18um CMOS Standard Cell Library using Synopsys Design Compiler. The synthesis result was about 11.9K logic gates and 1078 byte internal SRAM and the maximum operating frequency was 107Mhz. It consumes 879,617 clocks to process one QCIF frame, which means it can process 121.5 QCIF$(176\times144)$ frames per second, therefore it shows that it can be used for real time H.264/AVC encoding of various multimedia applications.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.5
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• pp.66-74
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• 2002

OFDM(Orthogonal Frequency Division Multiplexing)is a one of the nst promising digital modulation techniques adapted for Digital audio broadcasting or Digital TV since it is very robust against multipath fading channels. From 1997, since the OFDM technique was considered as the physical layer standard for the high data rate wireless LAN systems in the 5㎓ band, related studies have been studied actively. The key element to implement high data rate wireless LAN system using OFDM technique are IFFT and FFT modules. In this paper, new IFFT and FFT module are designed and implemented using current cut circuit based on the matrix-rounding process for the low-power consumptive operation and high-speed data processing. In addition to, we certify the available operation of the rounded IFFT/FFT module in the AWGN channel by using the BER performance simulation of IEEE 802.11TGa based OFDM modem with rounded IFFT/FFT module.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.39-44
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• 2003

As the portable electronic equipments are developed and popularized, the batteies are more important. To prolong life of the equipments, engineers demand to have batteries of high-power density and they are used to use Li-ion batteries popularly Li-ion batteries are better than conventional batteries, Ni-cd, about power density per volume and weight, but they have a fault that discharge voltage of them goes down. In order to maximize life of the Li-ion batterries, we have to use a converter which is suitable for the characteristic of Li-ion batteries. Therefore, capacitive idling SEPIC(Single Ended Primary Inductance Converter) that is derived from the SEPIC topology is proposed as a source of the Portable low-power applications. The converter has characteristics of buck-boost porformance. Besides, that makes it possible to increase the switching frequency by partial soft commutation of power switches through adding a diode and a switch. This paper is presented the characteristics, DC voltage conversion ratio, circuits of operation modes, of the converter and it is analized and implemented.

• Journal of Sensor Science and Technology
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• v.8 no.2
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• pp.163-170
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• 1999

A programmable A/D converter for an embedded fiber-optic combustion pressure sensor has been designed with 8 N and P channel MOSFETs, respectively. A local field enhancement for reducing programming voltage during writing as well as erasing an EEPROM device is introduced. In order to observe linear programmability of the EEPROM device during programming mode, a cell is developed with a $1.2\;{\mu}m$ double poly CMOS fabrication process in MOSIS. It is observed that the high resolution, of say 10mVolt, is valid in the range 1.25volts to 2volts. The experimental result is used for simulating the programmable 8 bit A/D converter with Hspice. The A/D converter is demonstrated to consume low power, $37\;{\mu}W$ by utilizing a programming operation. In addition, the converter is attained at the conversion frequency of 333 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.82-90
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• 2011

A novel class AB current subtracter(CS) and its application to Norton amplifier(NA) for low-power current-mode signal processing are designed. The CS is composed of a translinear cell, two current mirrors, and two common-emitter(CB) amplifiers. The principle of the current subtraction is that the difference of two input current applied translinear cell get from the current mirror, and then the current amplify through CB amplifier with ${\beta}$ times. The NA is consisted of the CS and wideband voltage buffer. The simulation results show that the CS has current input impedance of $20{\Omega}$, current gain of 50, and current input range of $i_{IN1}$ > $i_{IN2}{\geq}4I_B$. The NA has unit gain frequency of 312 MHz, transresistance of 130 dB, and power dissipation of 4mW at ${\pm}2.5V$ supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.1
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• pp.77-88
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• 2000

In this paper, the 3-mode variable gain high power amplifier for a transmitter of INMARSAT-B operating at L-band(1626.5-1646.5 MHz) was developed. This SSPA can amplify 42 dBm in high power mode, 38 dBm in medium power mode and 36 dBm in low power mode for INMARSAT-B. The allowable errol sets +1 dBm as the upper limit and -2 dBm as the lower limit, respectively. To simplify the fabrication process, the whole system is designed by two parts composed of a driving amplifier and a high power amplifier. The HP's MGA-64135 and Motorola's MRF-6401 were used for driving amplifier, and the ERICSSON's PTE-10114 and PTF-10021 for the high power amplifier. The SSPA was fabricated by the RP circuits, the temperature compensation circuits and 3-mode variable gain control circuits and 20 dB parallel coupled-line directional coupler in aluminum housing. In addition, the gain control method was proposed by digital attenuator for 3-mode amplifier. Then il has been experimentally verified that the gain is controlled for single tone signal as well as two tone signals. In this case, the SSPA detects the output power by 20 dB parallel coupled-line directional coupler and phase non-splitter amplifier. The realized SSPA has 41.6 dB, 37.6 dB and 33.2 dB for small signal gain within 20 MHz bandwidth, and the VSWR of input and output port is less than 1.3:1. The minimum value of the 1 dB compression point gets more than 12 dBm for 3-mode variable gain high power amplifier. A typical two tone intermodulation point has 36.5 dBc maximum which is single carrier backed off 3 dB from 1 dB compression point. The maximum output power of 43 dBm was achieved at the 1636.5 MHz. These results reveal a high power of 20 Watt, which was the design target.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.111-117
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• 2006

Reconfigurable CMOS low-noise amplifier (LAN) has been developed for multi-mode/multi-band wireless receiver. By employing common-gate input stage, the performance can be optimized for multiple operation bands by simply controlling the output load impedance. Although the conventional common-gate LAN has larger than 3dB noise figure (NF), the newly developed negative feedback scheme enables the common-gate input LNA to have less than 2dB NF. To have optimum linearity performance of wireless receiver, the gain of the LNA can be controlled. The LNA implemented in a 0.13mm CMOS technology shows $19{\sim}20dB$ voltage gain, $1.7{\sim}2.0dB$ NF, -2dBm iIP3 at $1.8{\sim}2.5GHz$ frequency range. The LNA dissipates 7mW from a 1.2V supply voltage.