• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.1
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• pp.53-60
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• 2010

This paper presents a novel gain control system composed of a feedback circuit, Two stage Low Noise Amplifier (LNA) using 0.18 um CMOS technology for 5.2 GHz. The feedback circuit consists of the seven function blocks: peak detector, comparator, ADC, IVE(Initial Voltage Elimination) circuit, switch, storage, and current controller. We focus on detecting signal and designing storage circuit that store the previous state. The power consumption of the feedback circuit in the system can be reduced without sacrificing the gain by inserting the storage circuit. The adaptive front-end system with the feedback circuit exhibits 11.39~22.74 dB gain, and has excellent noise performance at high gain mode. Variable gain LNA consumes 5.68~6.75 mW from a 1.8 V supply voltage.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2013.10a
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• pp.543-548
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• 2013

This paper presents a design of magnetorheological (MR) damper for control vibration of washing machine. This design is based on the requirements such as small dimensions with high damping force, and minimal consumed energy. The MR damper is designed using the shear mode of MR fluid, and Bingham plastic model is used for optimization process. In this design, a multi-coil design is adopted for damper to enhance damping force and reduce optimally structural parts. In optimization process, ADPL (Ansys Parametric Design Language) program is applied. Base on the optimal parameters, MR damper is manufactured and tested. In evaluation of MR damper, a modified sliding mode control is formulated and applied in both simulation and experiment. Results of experiment show that the MR damper satisfy the requirement of damping force for vibration control of washing machine.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.05a
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• pp.104-107
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• 2021

전 세계적으로 건조한 지역이 늘어남에 따라 산불 발생 빈도가 증가하고 있다. 이에 대한 대안으로 센서를 이용한 산불 감지 시스템의 연구가 이루어지고 있다. 기존의 서버가 센서의 작동시간 설정값을 보내는 방식은 산불 발생 빈도가 높은 환경에서는 산불 감지가 늦어지고 산불 발생 빈도가 낮은 환경에서는 불필요한 산불 감지로 센서의 생명주기 낮아지는 비효율적인 면이 있다. 이에 본 논문에서는 센서 기반 산불 감지 시스템을 위한 향상된 센싱 주기 기법을 제안한다. 제안하는 센싱 주기 기법은 환경 요인, 센서의 작동시간 알고리즘을 이용하여 환경에 맞는 센서의 작동시간 설정값을 결정한다. 그 후 센서의 화재 감지 알고리즘을 통해 센서는 서버로부터 설정값을 받아 운용모드로 전환하여 화재상황이 났을 시에 서버로 메세지를 보낸 후 생명주기를 위해 저전력모드로 전환한다. 성능평가를 통해 기존의 방식보다 평균 18.1분 빠르게 화재상황을 감지할 수 있고 소모전력도 2.2mA만큼 낮았다. 향우 실제 화재환경에서의 성능평가가 필요하다.

• Journal of the Korea Society of Computer and Information
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• v.20 no.4
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• pp.77-85
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• 2015

Recently, wireless sensor network(WSN) have been used in various fields to implement ubiquitous computing environment. WSN uses small, low cost and low power sensors in order to collect information from the sensor field. This paper proposes a clustering algorithm for energy efficiency of sensor nodes. The proposed algorithm is based on conventional LEACH, the representative clustering protocol for WSN and it prolongs network and nodes life time using sleep technique and changable transmission mode. The nodes of the proposed algorithm first calculate their clustering participation value based on the distance to the neighbor nodes. The nodes located in high density area will have clustering participation value and it can turn to sleep mode. Besides, proposed algorithm can change transmission method from conventional single-hop transmission to multi-hop transmission according to the energy level of cluster head. Simulation results show that the proposed clustering algorithm outperforms conventional LEACH, especially non-uniformly deployed network.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.6
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• pp.17-24
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• 2013

The localization accuracy in wireless sensor networks using ranging-based localization algorithms is greatly influenced by the ranging accuracy. Software implementation of HAL(Hardware Abstraction Layer) and MAC(Medium Access Layer) should seamlessly deliver the raw performance of ranging-based localization provided by hardware capability fully to the applications without degrading the raw performance. This paper presents the design and implementation of the software stack for IEEE 802.15.4a which supports normal ranging mode of the Nanotron's NA5TR1 RF chip. The experiment results shows that average ranging error rate with our implementation is 24.5% for the normal mode of the SDS-TWR ranging scheme.

• Journal of the Korea Society for Simulation
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• v.25 no.3
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• pp.1-14
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• 2016

This paper proposes four general wireless gateway types, which are distinguished by their own processing ways to connect between a wireless sub-network of things and the mobile internet that links mobile network to internet step by step. In this paper, we also design general processing procedures of these four types using the state transition model. Gateways of each types were developed on the basis of the resulted state transition models and their performances were evaluated through several tests, analyzed, and compared each other. As the results of our evaluation, compared with the other types, the type, which combines both of a low-power Sleep-interrupt way and polling ways for receiving data or responses in all the waiting states of a gateway, shows the best performance in all of data transmission real-timeliness, data loss and energy consumption.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.7
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• pp.105-116
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• 2004

The design of pico-/nano-satellites is particularly challenging due to constraints in mass, volume, power, and surface area. An efficient low-cost picosatellite HAUSAT-1 Electrical Power Subsystem (EPS) is developed to supply the power for various loads during the full mission life. This paper addresses design and analysis results of solar arrays, batteries, power conditioning and distribution units. The component selection, manufacturing and test results are presented by considering appropriate development cost and performance. The simulation results of power system are also illustrated, according to operational modes, through energy balance analysis. Finally, the EFS design feasibility is verified by comparing analysis results with functional and environmental test results at the system and component levels, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1868-1876
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• 2010

In this paper, we design a 256-bit EEPROM IP using only logic process-based devices. We propose EEPROM core circuits, a control gate (CG) and a tunnel gate (TG) driving circuit, to limit the voltages between the devices within 5.5V; and we propose DC-DC converters : VPP (=+4.75V), VNN (-4.75V), and VNNL (=VNN/3) generation circuit. In addition, we propose switching powers, CG_HV, CG_LV, TG_HV, TG_LV, VNNL_CG, VNNL_TG switching circuit, to be supplied for the CG and TG driving circuit. Simulation results under the typical simulation condition show that the power consumptions in the read, erase, and program mode are $12.86{\mu}W$, $22.52{\mu}W$, and $22.58{\mu}W$ respectively. Furthermore, the manufactured test chip operated normally and generated its target voltages of VPP, VNN, and VNNL as 4.69V, -4.74V, and -1.89V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1835-1839
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• 2008

Power management is a very important issue in portable electronic applications. Portable electronic devices require very efficient power management like LDO to increase the battery life. As the voltage variation of battery power is large in the application of cell phone, camera, laptop, automotive, industry application and so on, battery power is not directly used and LDO is used to supply the power of internal circuit. Besides, LDO can supply DC voltage that is lower than bauer voltage and constant DC voltage that is not related to largely fluctuated battery power. In the study, the power-save mode current and IR-drop characteristics are analyzed from a LDO with on-chip fabricated in 0.18-um CMOS technology.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.53-58
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• 2008

This paper designs sigma-delta D/A Converter with a high resolution and low power consumption. It reorganizes the input data along LJ, RJ, I2S mode and bit mode to the output data of A/D converter. The D/A converter decodes the original analog signal through HBF, Hold and 5th CIFB(Cascaded Integrators with distributed Feedback as well as distributed input coupling) sigma-delta modulation blocks. It uses repeatedly the addition operation in instead of the multiply operation for the chip area and the performance. Also, the half band filters of similar architecture composed the one block and it used the sample-hold block instead of the sinc filter. We supposed simple D/A Converter decreased in area. The filters of the block analyzed using the matlab tool. The top block designed using the top-down method by verilog language. The designed block is fabricated using Samsung 0.35um CMOS standard cell library. The chip area is 1500*1500um.