• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.19-27
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• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.3
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• pp.65-70
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• 2023

In recent years, the digital media environment has begun to diversify, with a greater focus being placed on user-centric design. With the development of digital technology, the digital media environment has formed a vast network of information, which supports interactive communication between people, creating a need for user-centric research. Mobile displays, as a representation of the digital media environment, have the advantage of mobility through the use of thin screen displays and low-performance image sensors, which allow for miniaturization and power saving. However, this results in reduced colour accuracy compared to large displays. This study investigates users' colour perception when using dark and light mode mobile displays. Colour perception was measured using a psycho-physical experiment, which controls each colour attribute based on the 12 colours of KS. The results were analysed to determine whether there is a difference in colour perception between dark mode and light mode, and if the difference was statistically significant. Future research directions based on the results are then discussed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.358-365
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• 2008

A differential-gain-controlled LNA is designed and implemented in 0.18 um CMOS technology for $3.1{\sim}4.8GHz$ UWB system. In high gain mode, measurements show a differential power gain of $14.1{\sim}15.8dB,\;13.3{\sim}15dB$, respectably, an input return loss higher then 10dB, an input IP3 of -19.3 dBm, a noise figure of $4.85{\sim}5.09dB$, while consuming only 19.8 mW of power from a 1.8V DC supply. In low gain mode, measurements show a differential power gain of $-6.1{\sim}-4.2dB,\;-7.6{\sim}-5.6dB$, respectably, an input return loss higher then 10dB, an input IP3 of -1.45 dBm, a noise figure of $8.8{\sim}10.3dB$, while consuming only 5.4mW of power from a 1.8V DC supply.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.5
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• pp.463-470
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• 2006

This paper deals with a new 3-phase power quality disturbance generator. The proposed generator can provide phase jump as well as voltage sag, swell, outage, unbalance, and over and under voltage. The operating principle of the generator is described in each mode of disturbance. The magnitude of the phase jump is analysed and it is found that the magnitude is the function of the turn-ratios of the transformers consisting the generator. The scheme has simple structure compared with the conventional one, and the major components of the proposed scheme are SCR thyristor and transformer, which guarantees high reliability and cost-effective implementation of the generator. Furthermore, high efficiency can be obtained because there is no PWM switching of the semiconductor devices, and it is easy to control the system. Simulations are carried out to confirm the operation in each disturbance mode, and experiments has been done with 5kVA power rating. The usefulness of the proposed scheme is verified through simulation and experimental results. It is expected that the scheme can be applied to the performance test of the custom power devices such as UPS, DVR, DSTATCOM, and SSTS with cost-effective system.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.64-72
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• 1998

In this paper, the design of a current integrator for low-voltage, low-power, and high frequency applications using complementary high swing cascode current-mirror is presented. The proposed integrator decreases output current errors due to non-zero input resistance and non-infinite output resistance of the simple current integrator. As a design example, the 3rd order Butterworth lowpass filter is designed by a leapfrog method. Also, we apply the predistortion design method to reduce the magnitude distortion which occurs at a cutoff frequency by the undesirable phase shift of a lossless current integrator. The designed current-mode filter is simulated and examined by SPICE using 0.8$\mu\textrm{m}$ CMOS n-well process parameters. The simulation results show 20MHz cutoff frequency and 615㎼ power dissipation with a 2V power supply. And the cutoff frequency of the filters can be easily changed by the DC bias current.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.3
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• pp.331-335
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• 2010

Previous low-energy time synchronization methods have mainly focused on reducing the number of transmission or reception packets. However, this paper proposes a method that reduces the percentage of time a node has to be awake (the duty cycle), assuming that a periodic sleep-wake cycle is used to conserve energy. Based on our experience with actual WSN devices, a system model is proposed, and the potential performance of the proposed method, with different parameter values, is analyzed. To further demonstrate the feasibility of our method, experiments were conducted using nine WSN devices in a $3{\times}3$ grid network topology. The results show the average synchronization error is 107.57 $\mu{s}$ in duty cycle 5% and synchronization period 10 sec, and 130 $\mu{s}$ in duty cycle 2.5% and synchronization period 20 sec.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.117-122
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• 2016

In this paper, we propose 24-GHz CMOS radio frequency (RF) power amplifier for short-range automotive collision avoidance radars. This circuit contains common source stage with inter-stages conjugate matching circuit as a class-A mode amplifier. The proposed circuit is designed using TSMC $0.13-{\mu}m$ mixed signal/RF CMOS process ($f_T/f_{MAX}=120/140GHz$). It operates at the supply voltage of 2V, and it is designed to have high power gain, low insertion loss and low noise figure in the low supply voltage. To reduce total chip area, the circuit used transmission lines instead of the bulky real inductor. The designed CMOS power amplifier showed the smallest chip size of $0.1mm^2$, the lowest power consumption of 40mW, the highest power gain of 26.5dB, the highest saturated output power of 19.2dBm and the highest maximum power-added efficiency of 17.2% as compared to recently reported results.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.7
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• pp.60-66
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• 2005

This paper presents the single-stage TSFC(Two-Switch Forward Converter). Recently, due to growing concern about the harmonic pollution of power distribution systems and the adoption of standards such as ICE 61000-3-2 and IEEE 519, There is a need to reduce the harmonic contests of AC line currents of power supplies. This research proposed the single-stage two switch forward circuit for low voltage and high current output. The principle of operation, feature and design considerations is illustrated and verified through the experiment with a 200[W](5[V], 40[A]) 100[kHz] MOSFET based experimental circuit.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.1
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• pp.91-96
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• 2018

In this paper, dual axes waveguide rotary joint, which operates at high power and has low loss characteristic, is designed and fabricated for a Ka-band millimeter-wave small radar. Its electrical performance is verified through the S-parameter at room temperature, high power and operation temperature test. Rotary joint functionally consists of the mode converter transforming rectangular waveguide into circular waveguide and the choke at the rotation part. At the configuration design, linking a fixed transmitter to an antenna rotating dual axes electrically for minimum loss and light weight body are considered. In Fc(center frequency)${\pm}500MHz$, the designed rotary joint has VSWR 1.5:1 below return loss, -2.0 dB above insertion loss. It is found that rotary joint characteristics is similar to design results.

• Journal of Advanced Navigation Technology
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• v.13 no.1
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• pp.48-53
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• 2009

The CMOS RF front-end for Global Positioning System(GPS)are implemented in 1P8M CMOS $0.13{\mu}m$ process. The LNAs consist of LNA1 with high gain and low NF, and LNA2 with low gain and high IIP3 for supporting operation with active and passive antenna. the measured performances of both LNAs are 16.4/13.8 dB gain, 1.4/1.68 dB NF, and -8/-4.4 dBm IIP3 with 3.2/2 mA form 1.2 V supply, respectively. The quadrature downconversion mixer is followed by transimpedance amplifier with gain controllability from 27.5 to 41 dB. The front-end performances in LNA1 mode are 39.8 dB conversion gain, 2.2 dB NF, and -33.4 dBm IIP3 with 6.6 mW power consumption.