• Journal of KIISE:Computer Systems and Theory
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• v.36 no.5
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• pp.422-428
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• 2009

NAND flash memory is widely used in embedded systems because of many attractive features, such as small size, light weight, low power consumption and fast access speed. However, it requires garbage collection, which includes erase operations. Erase operation is slower than other operations. Further, a block has a limited erase lifetime (typically 100,000) after which a block becomes unusable. The proposed garbage collection policy focuses on minimizing the total number of erase operations, the deviation value of each block and the garbage collection time. NAND flash memory consists of pages of three types, such as valid pages, invalid pages and free pages. In order to achieve above goals, we use a page ratio to decide when to do garbage collection and to select the target victimblock. Additionally, we implement allocating method and group management method. Simulation results show that the proposed policy performs better than Greedy or CAT with the maximum rate 85% of reduction in the deviation value of the erase operations and 6% reduction in garbage collection time.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.463-475
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• 2009

Flash memory is suitable for real time systems because of its consistent performance for random access, low power consumption and shock resistance. However, flash memory needs blocking time to perform a garbage collection to reclaim invalidated pages. Moreover, the worst-case garbage collection time is significantly longer than the best-case garbage collection time. In this paper, we propose a FTL (Flash Translation Layer) mapping scheme called KAST (K-Associative Sector Translation). In the KAST scheme, user can control the maximum association of the log block to limit the worst-case garbage collection time. Performance evaluation using simulation shows that not only KAST completes the garbage collection within the specified time but also provides about 10~15% better average performance than existing FTL schemes.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.451-462
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• 2009

Recently, there are many active studies to enhance low I/O performance of hard disk device. The studies on the hardware make good progress whereas those of the system software to enhance I/O performance may not support the hardware performance due to its poor progress. In this paper, we propose a new method of prefetching n-blocks into the flash memory. The proposed method consists of three steps: (1)analyzing the pattern of read requests in block units; (2)determining the number of blocks prefetched to flash memory; (3)replacing blocks according to block replacement policy. The proposed method can reduce the latency time of hard disk and optimize the power consumption of the computer system. Experimental results show that the proposed dynamic n-block method provides better average response time than that of the existing AMP(Adaptive multi stream prefetching) method by 9.05% and reduces the average power consumption than that of the existing AMP method by 11.11%.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.634-641
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• 2006

Flash memory has many advantages like non-volatility and fast I/O speed, but it has also disadvantages such as not-in-place-update data and asymmetric read/write/erase speed. For the performance of flash memory storage, it is essential for the buffer replacement algorithms to reduce the number of write operations that also affects the number of erase operations. A new buffer replacement algorithm is proposed in this paper, that delays the writes of not-cold-dirty pages in the buffer cache of flash storage. We show that this algorithm effectively decreases the number of write operations and erase operations without much degradation of hit ratio. As a result overall performance of flash I/O speed is improved.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.8
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• pp.807-812
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• 2015

Li-ion batteries are energy sources that are widely used in applications such as notebooks, cellular phones, power tools, and vehicles. They are devices in which stored chemical energy is changed to electrical energy by electrochemical reactions. They have a high energy density, small size, and are lightweight. In particular, power tools and vehicles require high charge/discharge rates. Therefore, in this paper, we perform electrochemical simulations using a commercial finite-element analysis program to determine the high discharge-rate characteristics of Li-ion cells. In addition, by performing high discharge-rate simulations, we found that the limited discharge current was 63 A. Based on the results obtained, we investigate the behavior of Li-ion cells with a high rate of discharge.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.169-169
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• 2011

STT-MRAM (수직자화 자기메모리)는 자화반전 현상을 원리로 구동하는 비휘발성 메모리로 기존의 메모리 장치에 비해 빠른 접근 속도와 높은 저장 밀도를 가지며 영구적인 기록이 가능하다. 이러한 장점들에 더해 적은 소모 전력을 지니므로 기존의 SRAM등의 한계를 극복할 대안으로 각광받고 있으며 차세대 메모리 군의 선두주자로 가장 적합한 후보중 하나이다. STT-MRAM의 건식 식각 방식에 있어 가장 큰 이슈는 소자 구동에 핵심적인 역할을 하는 MTJ(Magnetic Tunnel Junction)의 식각이다. MTJ는 free layer, tunnel barrier, pinned layer 3개의 층으로 구성되어 있으며 양 끝 layer에는 강자성체인 CoFeB가 사용되고 tunnel barrier에는 절연층인 MgO가 사용되고 있다. 이러한 물질들은 기존의 반도체 소자에서는 사용되지 않았던 물질들로 기존 공정에서 사용되던 Cl2 based plasma etching에서는 측벽에 비화발성 반응물과 잔류 Cl2에 의해 부식이 발생하는 문제점이 드러나고 있다. 이러한 문제점을 해결하기 위한 새로운 대안으로 CO/NH3/Ar나 CH4/Ar 같은 새로운 가스 조합을 사용하는 연구가 진행되고 있다. 이러한 연구에 의해 기존의 Cl2 plasma를 이용한 식각에서 나타나는 문제점은 해결이 되었으나 또 다른 문제점들이 보고되고 있다. 본 연구에서는 stack MRAM sample을 사용하여 기존의 사용되는 Cl2/Ar plasma와 대안 gas인 CO/NH3, CH4/Ar plasma에서의 식각을 진행하였으며 실험 조건(gas 비율 변화, Bias power 변화, 식각 시간)에 따른 식각 속도의 변화나 식각 후의 profile에 대하여 관찰하였다. 이에 따라 식각후에 어떠한 차이점이 있는 지를 알아보았으며 CO/NH3나 CH4/Ar plasma에서 식각시 나타나는 문제점에 대하여도 조명해 보았다.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.6
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• pp.587-593
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• 2011

A new high power density and low cost Photovoltaic Power Conditioning System (PV PCS) with energy storage system is proposed. Its high power density and cost effectiveness can be achieved through the unification of the maximum power point tracker and battery charger/discharger. Despite of the reduced power stage, the proposed system can achieve the same performances of maximum power point tracking and battery charging/discharging as the conventional system. Moreover, the high voltage stress across the link-capacitor can be relieved through the series-connected link-capacitor with the battery. Therefore, a large number of series/parallel-connected link-capacitors can be reduced by 4-times. Especially, when the utility power failure happens, both photovoltaic and battery energies can be supplied to the load with only one power stage. Therefore, it features a simpler structure, less mass, lower cost, and fewer devices. Finally, to confirm the operation, validity, and features of the proposed system, theoretical analysis and experimental results from a single phase AC 220Vrms/1.5kW prototype are presented.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.10
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• pp.413-420
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• 2013

Redundant arrays of independent disks (RAID) without a power-fail-safe component in small and mid-sized business suffers from intolerably long resynchronization time after a unclean power-failure. Data blocks and a parity block in a stripe must be updated in a consistent manner, however a data block may be updated but the corresponding parity block may not be updated when a power goes off. Such a partially modified stripe must be updated with a correct parity block. However, it is difficult to find which stripe is partially updated (inconsistent). The widely-used traditional parity resynchronization manner is a intolerably long process that scans the entire volume to find and fix inconsistent stripes. This paper presents a fast resynchronization scheme with a negligible overhead for small and mid-sized RAIDs. The proposed scheme is integrated into a software RAID driver in a Linux system. According to the performance evaluation, the proposed scheme shortens the resynchronization process from 200 minutes to 5 seconds with 2% overhead for normal I/Os.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.10
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• pp.582-588
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• 2002

Scalable displays generate large and high resolution images and provide an immersive environment. Recently, scalable displays are built on the networked clusters of PCs, each of which has a fast graphics accelerator, memory, CPU, and storage. However, the distributed rendering on clusters is a network bound work because of limited network bandwidth. In this paper, we present a new algorithm for reducing the network bandwidth and implement it with a conventional distributed rendering system. This paper describes the algorithm called geometry tracking that avoids the redundant geometry transmission by indexing geometry data. The experimental results show that our algorithm reduces the network bandwidth up to 42%.

• The KIPS Transactions:PartD
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• v.14D no.7
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• pp.719-726
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• 2007

Recently, NAND flash memory has been used for a storage device in various mobile computing devices such as MP3 players, mobile phones and laptops because of its shock-resistant, low-power consumption, and none-volatile properties. However, due to the very distinct characteristics of flash memory, disk based systems and applications may result in severe performance degradation when directly adopting them on flash memory storage systems. Especially, when a B-tree is constructed, intensive overwrite operations may be caused by record inserting, deleting, and its reorganizing, This could result in severe performance degradation on NAND flash memory. In this paper, we propose an efficient buffer management scheme, called IBSF, which eliminates redundant index units in the index buffer and then delays the time that the index buffer is filled up. Consequently, IBSF significantly reduces the number of write operations to a flash memory when constructing a B-tree. We also show that IBSF yields a better performance on a flash memory by comparing it to the related technique called BFTL through various experiments.